CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

14

POST OFFICE BOX 655303

APPLICATION INFORMATION

LVPECL receiver input termination

The input of the CDCP1803 has a high impedance and comes with a large common-mode voltage range.

For optimized noise performance, it is recommended to properly terminate the PCB trace (transmission line).

If a differential signal drives the CDCP1803, then a 100-

Ω termination resistor is recommended to be placed

as close as possible across the input pins. An even better approach is to install 2x 50

Ω, with the center tap

connected to a capacitor (C) to terminate odd-mode noise and make up for transmission line mismatches. The

IN

LVPECL

150

Ω

150

Ω

CAC

CAC

50

Ω

50

Ω

IN

CDCP1803

C

VBB

50

Ω

50

Ω

Figure 9. Recommended AC-Coupling LVPECL Receiver Input Termination

LVPECL

130

Ω

83

Ω

CDCP1803

50

Ω

50

Ω

130

Ω

83

Ω

Figure 10. Recommended DC-Coupling LVPECL Receiver Input Termination