CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

17

POST OFFICE BOX 655303

APPLICATION INFORMATION

enabling a single output stage

If a single output stage becomes enabled:

With the first positive clock transition the undivided output becomes the input clock state. The divided output

states are equal to the actual internal divider. The internal divider doesn’t get reset while enabling single output

drivers.

High-Z

ENABLE Yx:

IN

Yx:/1

High-Z

Yx:/x

Undefined

Enabled

Disabled

Divider State

Undivided State is Valid After the First

Positive Transition of the Input Clock

Undefined

Figure 13. Signal State After an Output Driver Becomes Enabled While IN = 0

High-Z

ENABLE Yx:

IN

Yx:/1

Undefined

High-Z

Yx:/x

Undefined

Divider State

Enabled

Disabled

Undivided State is Valid After the First

Positive Transition of the Input Clock

Figure 14. Signal State After an Output Driver Becomes Enabled While IN = 1