CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

12

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

|Yn

*Yn|

Yn

Yn

VOH

VOL

80%

20%

0 V

tr

tf

VOUT(pp)

Figure 7. LVPECL Differential Output Voltage and Rise/Fall Time

PCB design for thermal functionality

It is recommended to take special care of the PCB design for good thermal flow from the MLF-24 pin package

to the PCB.

Due to the three LVPECL outputs, the current consumption of the CDCP1803 is fixed.

JEDEC JESD51-7 specifies thermal conductivity for standard PCB boards.

Modeling the CDCP1803 with a standard 4-layer JEDEC board results into a 59.5

°C max temperature with a

When deploying four thermal vias (one per quadrant), the thermal flow improves significantly, yielding 42.9

°C

max temperature with a

To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications enabling

all four outputs at ones.