AD5675R datasheet(8/28 Pages) AD

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Data Sheet

AD5676

Rev. B | Page 7 of 27

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4.

VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, VREF = 2.5 V, all specifications −40°C to +125°C, unless otherwise noted.

Table 5.

1.8 V ≤ VLOGIC < 2.7 V

2.7 V ≤ VLOGIC ≤ 5.5 V

Parameter1

Symbol

Min

Max

Min

Max

Unit

SCLK Cycle Time

120

83.3

SCLK High Time

25.3

SCLK Low Time

2.8

3.25

SYNC to SCLK Falling Edge

Data Setup Time

1.2

0.5

Data Hold Time

0.3

0.4

SCLK Falling Edge to SYNC Rising Edge

16.2

Minimum SYNC High Time

55.1

SDO Data Valid from SCLK Rising Edge

t10

21.5

22.7

SCLK Falling Edge to SYNC Rising Edge

t11

24.4

20.3

SYNC Rising Edge to SCLK Rising Edge

t12

85.5

Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.

Circuit Diagram and Daisy-Chain and Readback Timing Diagrams

200µA

IOL

200µA

IOH

VOH (MIN)

TO OUTPUT

20pF

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

SDO

SDI

SYNC

SCLK

DB23

DB0

DB23

DB0

DB23

INPUT WORD FOR DAC N

UNDEFINED

INPUT WORD FOR DAC N + 1

INPUT WORD FOR DAC N

DB0

t11

t12

t10

Figure 4. Daisy-Chain Timing Diagram

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