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AD5676

Data Sheet

Rev. B | Page 24 of 27

HARDWARE RESET (RESET)

The RESET pin is an active low reset that allows the outputs to

be cleared to either zero scale or midscale. The clear code value

is user selectable via the RESET select pin. It is necessary to keep

the RESET pin low for a minimum time (see Table 4) to complete

the operation (see Figure 2). When the RESET signal is returned

high, the output remains at the cleared value until a new value is

programmed. While the RESET pin is low, the outputs cannot be

updated with a new value. A software executable reset function

is also available that resets the DAC to the power-on reset code.

Command 0110 is designated for this software reset function

(see Table 9). Any events on the LDAC or RESET pins during

power-on reset are ignored.

RESET SELECT PIN (RSTSEL)

The AD5676 contains a power-on reset circuit that controls the

output voltage during power-up. By connecting the RSTSEL pin

low, the output powers up to zero scale. Note that this is outside

the linear region of the DAC; by connecting the RSTSEL pin

high, VOUTx power up to midscale. The output remains powered

up at this level until a valid write sequence is made to the DAC.

The RSTSEL pin is only available on the TSSOP package. When

the AD5676 LFCSP package is used the outputs power up to 0 V.

AMPLIFIER GAIN SELECTION ON LFCSP PACKAGE

The output amplifier gain setting for the LFCSP package is

determined by the state of Bit DB2 in the Gain setup register

(see Table 16 and Table 17).

Table 16. Gain Setup Register

Bit

Description

DB2

Amplifier gain setting

DB2 = 0; amplifier gain = 1 (default)

DB2 = 1; amplifier gain = 2

Table 17. 24-Bit Input Shift Register Contents for Gain Setup Command

DB23 (MSB)

DB22

DB21

DB20

DB19 to DB3

DB2

DB1

DB0 (LSB)

Don’t care

Gain

Reserved; set to 0

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