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AD5676

Data Sheet

Rev. B | Page 22 of 27

READBACK OPERATION

Readback mode is invoked through a software executable

readback command. If the SDO output is disabled via the daisy-

chain mode disable bit in the control register, it is enabled

automatically for the duration of the read operation, after which

it is disabled again. Command 1001 is reserved for the readback

function. This command, in association with the address bits,

A3 to A0, selects the DAC input register to read. Note that,

during readback, only one DAC register can be selected. The

remaining data bits in the write sequence are don’t care bits.

During the next SPI write, the data appearing on the SDO output

contains the data from the previously addressed register.

For example, to read back the DAC register for Channel 0,

implement the following sequence:

1. Write 0x900000 to the AD5676 input register. This

configures the device for read mode with the DAC register

of Channel 0 selected. Note that all data bits, DB15 to DB0,

are don’t care bits.

2. Follow this with a second write, a no operation (NOP)

condition, 0x000000. During this write, the data from the

contain undefined data, and the last 16 bits contain the

DB19 to DB4 DAC register contents.

When SYNC is high the SDO pin is driven by a weak latch

which holds the last data bit. The SDO pin can be overdriven by

the SDO pin of another device, thus allowing multiple devices

to be read using the same SPI interface.

POWER-DOWN OPERATION

The AD5676 provides two separate power-down modes.

Command 0100 is designated for the power-down function (see

Table 9). These power-down modes are software programmable

by setting 16 bits, Bit DB15 to Bit DB0, in the input shift register.

There are two bits associated with each DAC channel. Table 12

shows how the state of the two bits corresponds to the mode of

operation of the device.

Table 12. Modes of Operation

Operating Mode

PD1

PD0

Normal Operation

Power-Down Modes

1 kΩ to GND

Three-State

Any or all DACs (DAC 0 to DAC 7) power down to the selected

mode by setting the corresponding bits. See Table 13 for the

contents of the input shift register during the power-down/

power-up operation.

When both Bit PD1 and Bit PD0 in the input shift register are set to

0, the device works normally with its normal power consumption

of 1.1 mA typically. However, for the two power-down modes,

the supply current falls to 1 µA typically. Not only does the

supply current fall, but the output stage is also internally switched

from the output of the amplifier to a resistor network of known

values. This has the advantage that the output impedance of the

devices are known while the devices are in power-down mode.

There are two different power-down options. The output is

connected internally to GND through either a 1 kΩ resistor, or

it is left open-circuited (three-state). The output stage is shown in

Figure 45.

RESISTOR

NETWORK

VOUTx

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 45. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry shut down when power-down mode is

activated. However, the contents of the DAC register are

unaffected when in power-down. The DAC register updates

while the device is in power-down mode. The time required to

exit power-down is typically 5 µs for VDD = 5 V.

Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation1

[DB23:DB20]

DB19

[DB18:DB16]

DAC 7

DAC 6

DAC 5

DAC 4

DAC 3

DAC 2

DAC 1

DAC 0

[DB15: B14]

[DB13: B12]

[DB11: B10]

[DB9:DB8]

[DB7:DB6]

[DB5:DB4]

[DB3:DB2]

[DB1:DB0]

0100

XXX

[PD1:PD0]

X means don’t care.

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