AD5676

Data Sheet

Rev. B | Page 10 of 27

14

13

12

1

3

4

RESET

SDO

LDAC

11 GND

SYNC

2

SCLK

5

SDI

NIC = NOT INTERNALLY CONNECTED

AD5676

TOP VIEW

(Not to Scale)

Figure 6. 20-Lead LFCSP Pin Configuration

Table 8. 20-Lead LFCSP Pin Function Descriptions

Pin No.

Mnemonic

Description

1

0.1 µF capacitor to GND.

2

Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.

3

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data

transfers in on the falling edges of the next 24 clocks.

4

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data

transfers at rates of up to 50 MHz.

5

SDI

Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the falling edge of

the serial clock input.

6

Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.

7

Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.

8

Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.

9

Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.

10, 16

NIC

Not Internally Connected

11

GND

Ground Reference Point for All Circuitry on the Device.

12

LDAC

Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all

DAC registers to be updated if the input registers have new data. That allows all DAC outputs to simultaneously

update. This pin can also be tied permanently low.

13

SDO

Serial Data Output. This pin can be used to daisy-chain a number of devices together, or it can be used for

readback. The serial data transfers on the rising edge of SCLK and is valid on the falling edge.

14

RESET

Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.

When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending

on the state of the RSTSEL pin.

15

Reference Input Voltage.

17

Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.

18

Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.

19

Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.

20

Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.

EPAD

Exposed Pad. The exposed pad must be tied to GND.