8XC552 datasheet(52/60 Pages) PHILIPS

52 / 60 page

Philips Semiconductors

80C51 Family Derivatives

8XC552/562 overview

1996 Aug 06

ADC Resolution and Analog Supply: Figure 38 shows how the

ADC is realized. The ADC has its own supply pins (AVDD and AVSS)

and two pins (Vref+ and Vref–) connected to each end of the DAC’s

resistance-ladder. The ladder has 1023 equally spaced taps,

separated by a resistance of “R”. The first tap is located 0.5 x R

above Vref–, and the last tap is located 1.5 x R below Vref+. This

gives a total ladder resistance of 1024 x R. This structure ensures

that the DAC is monotonic and results in a symmetrical quantization

error as shown in Figure 40.

For input voltages between Vref– and (Vref–) + 1/2 LSB, the 10-bit

result of an A/D conversion will be 00 0000 0000B = 000H. For input

voltages between (Vref+) – 3/2 LSB and Vref+, the result of a

conversion will be 11 1111 1111B = 3FFH. AVref+ and AVref– may

be between AVDD + 0.2V and AVSS – 0.2V. AVref+ should be

positive with respect to AVref–, and the input voltage (Vin) should be

between AVref+ and AVref–. If the analog input voltage range is from

2V to 4V, then 10-bit resolution can be obtained over this range if

AVref+ = 4V and AVref– = 2V.

The result can always be calculated from the following formula:

Result

+ 1024

IN * AVref

ref

) * AVref*

Power Reduction Modes

The 8XC552 has two reduced power modes of operation: the idle

mode and the power-down mode. These modes are entered by

setting bits in the PCON special function register. When the 8XC552

enters the idle mode, the following functions are disabled:

CPU

(halted)

Timer T2

(halted and reset)

PWM0, PWM1

(reset; outputs are high)

ADC

(conversion aborted if in

progress).

In idle mode, the following functions remain active:

Timer 0

Timer 1

Timer T3

SIO0 SIO1

External interrupts

When the 8XC552 enters the power-down mode, the oscillator is

stopped. The power-down mode is entered by setting the PD bit in

the PCON register. The PD bit can only be set if the EW input is tied

HIGH.

Successive

Approximation

Control Logic

Successive

Approximation

–

Decoder

MSB

Comparator

LSB

Start

Ready

AVref+

AVref–

R/2

Total resistance

1023R + 2 x R/

1024R

Vref

Vin

1023

1022

1021

Value 0000 0000 00

is output for voltages Vref– to (Vref– + 1/2 LSB)

Value 1111 1111 11

is output for voltages (Vref+ – 3/2 LSB) to Vref+

Figure 38. ADC Realization

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