8XC552 datasheet(9/60 Pages) PHILIPS

9 / 60 page

Philips Semiconductors

80C51 Family Derivatives

8XC552/562 overview

1996 Aug 06

CTI0

BIT

SYMBOL

FUNCTION

TM2IR.7

T2OV

Timer T2 16-bit overflow interrupt flag

TM2IR.6

CMI2

CM2 interrupt flag

TM2IR.5

CMI1

CM1 interrupt flag

TM2IR.4

CMI0

CM0 interrupt flag

TM2IR.3

CTI3

CT3 interrupt flag

TM2IR.2

CTI2

CT2 interrupt flag

TM2IR.1

CTI1

CT1 interrupt flag

TM2IR.0

CTI0

CT0 interrupt flag

SU00761

CTI1

CTI2

CTI3

CMI0

CMI1

CMI2

T2OV

(LSB)

(MSB)

TM2IR (C8H)

Interrupt Flag Register (TM2IR)

PCT0

BIT

SYMBOL

FUNCTION

IP1.7

PT2

Timer T2 overflow interrupt(s) priority level

IP1.6

PCM2

Timer T2 comparator 2 interrupt priority level

IP1.5

PCM1

Timer T2 comparator 1 interrupt priority level

IP1.4

PCM0

Timer T2 comparator 0 interrupt priority level

IP1.3

PCT3

Timer T2 capture register 3 interrupt priority level

IP1.2

PCT2

Timer T2 capture register 2 interrupt priority level

IP1.1

PCT1

Timer T2 capture register 1 interrupt priority level

IP1.0

PCT0

Timer T2 capture register 0 interrupt priority level

PCT1

PCT2

PCT3

PCM0

PCM1

PCM2

PT2

(LSB)

(MSB)

IP1 (F8H)

Timer 2 Interrupt Priority Register (IP1)

Figure 8. Interrupt Flag Register (TM2IR) and Timer T2 Interrupt Priority Register (IP1)

Timer T3, The Watchdog Timer

In addition to Timer T2 and the standard timers, a watchdog timer is

also incorporated on the 8XC552. The purpose of a watchdog timer

is to reset the microcontroller if it enters erroneous processor states

(possibly caused by electrical noise or RFI) within a reasonable

period of time. An analogy is the “dead man’s handle” in railway

locomotives. When enabled, the watchdog circuitry will generate a

system reset if the user program fails to reload the watchdog timer

within a specified length of time known as the “watchdog interval.”

Watchdog Circuit Description: The watchdog timer (Timer T3)

consists of an 8-bit timer with an 11-bit prescaler as shown in Figure

9. The prescaler is fed with a signal whose frequency is 1/12 the

oscillator frequency (1MHz with a 12MHz oscillator). The 8-bit timer

is incremented every “t” seconds, where:

t = 12

× 2048 × 1/fOSC

(= 1.5ms at fOSC = 16MHz; = 1ms at fOSC = 24MHz)

If the 8-bit timer overflows, a short internal reset pulse is generated

which will reset the 8XC552. A short output reset pulse is also

generated at the RST pin. This short output pulse (3 machine

cycles) may be destroyed if the RST pin is connected to a capacitor.

This would not, however, affect the internal reset operation.

Watchdog operation is activated when external pin EW is tied low.

When EW is tied low, it is impossible to disable the watchdog

operation by software.

How to Operate the Watchdog Timer: The watchdog timer has to

be reloaded within periods that are shorter than the programmed

watchdog interval; otherwise the watchdog timer will overflow and a

system reset will be generated. The user program must therefore

continually execute sections of code which reload the watchdog

timer. The period of time elapsed between execution of these

sections of code must never exceed the watchdog interval. When

using a 16MHz oscillator, the watchdog interval is programmable

between 1.5ms and 392ms. When using a 24MHz oscillator, the

watchdog interval is programmable between 1ms and 255ms.

In order to prepare software for watchdog operation, a programmer

should first determine how long his system can sustain an

erroneous processor state. The result will be the maximum

watchdog interval. As the maximum watchdog interval becomes

shorter, it becomes more difficult for the programmer to ensure that

the user program always reloads the watchdog timer within the

watchdog interval, and thus it becomes more difficult to implement

watchdog operation.

The programmer must now partition the software in such a way that

reloading of the watchdog is carried out in accordance with the above

requirements. The programmer must determine the execution times

of all software modules. The effect of possible conditional branches,

subroutines, external and internal interrupts must all be taken into

account. Since it may be very difficult to evaluate the execution

times of some sections of code, the programmer should use worst

case estimations. In any event, the programmer must make sure

that the watchdog is not activated during normal operation.

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