8XC552 datasheet(22/60 Pages) PHILIPS

22 / 60 page

Philips Semiconductors

80C51 Family Derivatives

8XC552/562 overview

1996 Aug 06

SLA

Data

P or S

B0H

A8H

B8H

Reception of the Own

Slave Address and

Transmission of One or

More Data Bytes

Data

C0H

Any Number of Data Bytes and Their Associated Acknowledge Bits

This Number (Contained in S1STA) Corresponds to a Defined State of the I2C Bus. See Table 6.

Data

All “1”s

From Master to Slave

From Slave to Master

C8H

P or S

Last Data Byte Transmitted.

Switched to Not Addressed Slave

(AA Bit in S1CON = “0”

Arbitration Loast as MST and

Addressed as Slave

Figure 20. Format and States of the Slave Transmitter Mode

Master Receiver Mode: In the master receiver mode, a number of

data bytes are received from a slave transmitter (see Figure 18).

The transfer is initialized as in the master transmitter mode. When

the start condition has been transmitted, the interrupt service routine

must load S1DAT with the 7-bit slave address and the data direction

bit (SLA+R). The SI bit in S1CON must then be cleared before the

serial transfer can continue.

When the slave address and the data direction bit have been

transmitted and an acknowledgment bit has been received, the

serial interrupt flag (SI) is set again, and a number of status codes in

S1STA are possible. These are 40H, 48H, or 38H for the master

mode and also 68H, 78H, or B0H if the slave mode was enabled

(AA = logic 1). The appropriate action to be taken for each of these

status codes is detailed in Table 4. ENS1, CR1, and CR0 are not

affected by the serial transfer and are not referred to in Table 4. After

a repeated start condition (state 10H), SIO1 may switch to the

master transmitter mode by loading S1DAT with SLA+W.

Slave Receiver Mode: In the slave receiver mode, a number of

data bytes are received from a master transmitter (see Figure 19).

To initiate the slave receiver mode, S1ADR and S1CON must be

loaded as follows:

S1ADR (DBH)

XGC

own slave address

The upper 7 bits are the address to which SIO1 will respond when

addressed by a master. If the LSB (GC) is set, SIO1 will respond to

the general call address (00H); otherwise it ignores the general call

address.

S1CON (D8H)

ENS1

STA

STO

CR1

CR0

CR2

CR0, CR1, and CR2 do not affect SIO1 in the slave mode. ENS1

must be set to logic 1 to enable SIO1. The AA bit must be set to

enable SIO1 to acknowledge its own slave address or the general

call address. STA, STO, and SI must be reset.

When S1ADR and S1CON have been initialized, SIO1 waits until it

is addressed by its own slave address followed by the data direction

bit which must be “0” (W) for SIO1 to operate in the slave receiver

mode. After its own slave address and the W bit have been

received, the serial interrupt flag (I) is set and a valid status code

can be read from S1STA. This status code is used to vector to an

interrupt service routine, and the appropriate action to be taken for

each of these status codes is detailed in Table 5. The slave receiver

mode may also be entered if arbitration is lost while SIO1 is in the

master mode (see status 68H and 78H).

If the AA bit is reset during a transfer, SIO1 will return a not

acknowledge (logic 1) to SDA after the next received data byte.

While AA is reset, SIO1 does not respond to its own slave address

or a general call address. However, the I2C bus is still monitored

and address recognition may be resumed at any time by setting AA.

This means that the AA bit may be used to temporarily isolate SIO1

from the I2C bus.

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