8XC552 datasheet(8/60 Pages) PHILIPS

8 / 60 page

Philips Semiconductors

80C51 Family Derivatives

8XC552/562 overview

1996 Aug 06

interrupt requests are recognized during the following cycle. If these

flags are polled, a transition at CT0I or CT1I will be recognized one

cycle before a transition on CT2I or CT3I since registers are read

during S5. The CMI0, CMI1, and CMI2 flags are set during S6 of the

cycle following a match. CMI0 is scanned by the interrupt logic

during S2; CMI1 and CMI2 are scanned during S3 and S4. A match

will be recognized by the interrupt logic (or by polling the flags) two

cycles after the match takes place.

The 16-bit overflow flag (T2OV) and the byte overflow flag (T2BO)

are set during S6 of the cycle in which the overflow occurs. These

flags are recognized by the interrupt logic during the next cycle.

Special function register IP1 (Figure 8) is used to determine the

Timer T2 interrupt priority. Setting a bit high gives that function a

high priority, and setting a bit low gives the function a low priority.

The functions controlled by the various bits of the IP1 register are

shown in Figure 8.

CTP0

BIT

SYMBOL

CAPTURE/INTERRUPT ON:

CTCON.7

CTN3

Capture Register 3 triggered by a falling edge on CT3I

CTCON.6

CTP3

Capture Register 3 triggered by a rising edge on CT3I

CTCON.5

CTN2

Capture Register 2 triggered by a falling edge on CT2I

CTCON.4

CTP2

Capture Register 2 triggered by a rising edge on CT2I

CTCON.3

CTN1

Capture Register 1 triggered by a falling edge on CT1I

CTCON.2

CTP1

Capture Register 1 triggered by a rising edge on CT1I

CTCON.1

CTN0

Capture Register 0 triggered by a falling edge on CT0I

CTCON.0

CTP0

Capture Register 0 triggered by a rising edge on CT0I

SU00758

CTN1

CTP1

CTN1

CTP2

CTN2

CTP3

CTN3

(LSB)

(MSB)

CTCON (EBH)

Figure 5.

Capture Control Register (CTCON)

RP40

BIT

SYMBOL

FUNCTION

RTE.7

TP47

If “1” then P4.7 toggles on a match between CM1 and Timer T2

RTE.6

TP46

If “1” then P4.6 toggles on a match between CM1 and Timer T2

RTE.5

RP45

If “1” then P4.5 is reset on a match between CM1 and Timer T2

RTE.4

RP44

If “1” then P4.4 is reset on a match between CM1 and Timer T2

RTE.3

RP43

If “1” then P4.3 is reset on a match between CM1 and Timer T2

RTE.2

RP42

If “1” then P4.2 is reset on a match between CM1 and Timer T2

RTE.1

RP41

If “1” then P4.1 is reset on a match between CM1 and Timer T2

RTE.0

RP40

If “1” then P4.0 is reset on a match between CM1 and Timer T2

SU00759

RO41

RP42

RP43

RP44

RP45

TP46

TP47

(LSB)

(MSB)

RTE (EFH)

Figure 6.

Reset/Toggle Enable Register (RTE)

SP40

BIT

SYMBOL

FUNCTION

STE.7

TG47

Toggle flip-flops

STE.6

TG46

Toggle flip-flops

STE.5

SP45

If “1” then P4.5 is set on a match between CM0 and Timer T2

STE.4

SP44

If “1” then P4.4 is set on a match between CM0 and Timer T2

STE.3

SP43

If “1” then P4.3 is set on a match between CM0 and Timer T2

STE.2

SP42

If “1” then P4.2 is set on a match between CM0 and Timer T2

STE.1

SP41

If “1” then P4.1 is set on a match between CM0 and Timer T2

STE.0

SP40

If “1” then P4.0 is set on a match between CM0 and Timer T2

SU00760

SP41

SP42

SP43

SP44

SP45

TG46

TG47

(LSB)

(MSB)

STE (EEH)

Figure 7. Set Enable Register (STE)

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