CS53L30 datasheet(48/67 Pages) CIRRUS

48 / 67 page

DS992F2

CS53L30

7.6 MCLK Control

DISCHARGE_

FILT+

Discharge FILT+ capacitor. Configures the state of the FILT+ pin internal clamp. Before setting this bit, ensure that the

VA pin is connected to a supply, as described in Table 3-1.

0 (Default) FILT+ is not clamped to ground.

1 FILT+ is clamped to ground. This must be set only if PDN_ULP or PDN_LP = 1. Discharge time with an external

2.2-µF capacitor on FILT+ is ~46 ms.

THMS_PDN Thermal-sense power down. Configures the state of the power sense circuit.

0 Powered up.

1 (Default) Powered down.

3:0

—

Reserved

7.6 MCLK Control

Address 0x07

R/W

54321

MCLK_DIS

MCLK_INT_SCALE DMIC_DRIVE

—

MCLK_DIV[1:0]

SYNC_EN

—

Default

0010

Bits

Name

Description

MCLK_DIS Master clock disable. Configures the state of the internal MCLK signal prior to its fanout to all internal circuitry.

0 (Default) On

1 Off; Disables the clock tree to save power when the device is powered down and the external MCLK is running.

Note: The external MCLK must be running whenever this bit is altered.

6MCLK_INT_

SCALE

Internal MCLK scaling enable. Allows internal modulator rate to be scaled with the ASP_RATE setting to save power.

0 (Default) Off. MCLKINT and FsINT divide-ratio is 1.

1 On. Enables internal MCLK and FsINT scaling. MCLKINT and FsINT divide ratio is either 2 or 4, depending on ASP_

RATE and INTERNAL_FS_RATIO settings (see Table 4-2).

5DMIC_

DRIVE

DMIC clock output drive strength. Selects the drive strength used for the DMICx clock outputs. Table 3-14 describes

drive-strength specifications.

0 (Default) Normal

1 Decreased

4—

Reserved

3:2 MCLK_DIV Master clock divide ratio. Selects the divide ratio between the selected MCLK source and the internal MCLK (MCLKINT).

Table 4-2 lists supported MCLK rates and their associated programming settings.

00 Divide by 1

01 (Default) Divide by 2

10 Divide by 3

11 Reserved

• This field must be changed only if PDN_ULP or PDN_LP = 1 and MCLK_DIS = 1.

• The control port’s autoincrement feature is not supported on this bit field.

SYNC_EN Multichip synchronization enable. Toggle high to enable synchronization sequence.

0)(Default) No activity

1)Begins multichip synchronization sequence. To restart the sequence this bit must be cleared and then set.

0—

Reserved

7.7 Internal Sample Rate Control

Address 0x08

R/W

321

—

INTERNAL_FS_RATIO

—

MCLK_19MHZ_EN

Default

Bits

Name

Description

7:5

—

Reserved

INTERNAL_

FS_RATIO

Internal sample rate (Fsint). Selects the divide ratio from MCLKINT to produce the internal sample rate used for all

converters. Slave/Master Mode is determined by ASP_M/S on p. 49.

0MCLKINT/125

1 (Default) MCLKINT/128

3:1

—

Reserved

0MCLK_

19MHZ_EN

19.2-MHz MCLK enable. (Slave/Master Mode is determined by ASP_M/S on p. 49.)

0 (Default) MCLK

19.2 MHz

1MCLK = 19.2 MHz

Bits

Name

Description

CS53L30 Datasheet(PDF) 48 Page - Cirrus Logic

CS53L30 Datasheet(HTML) 48 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Datasheet Download

Link URL