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CS43130 Datasheet(PDF) 71 Page - Cirrus Logic |
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CS43130 Datasheet(HTML) 71 Page - Cirrus Logic |
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71 / 137 page  DS1073F1 71 CS43130 5.10 Example Sequences 31 Configure DSD interface DSD Interface Configuration. 0x70003 0x04 Reserved DSD_M/SB DSD_PM_EN DSD_PM_SEL 0000 0 1 0 0 DSD is clock master Function is disabled Function is disabled 32 Configure DSD Path Signal Control 2 DSD Processor Path Signal Control 2. 0x70004 0x50 Reserved DSD_PRC_SRC DSD_EN Reserved DSD_SPEED STA_DSD_DET INV_DSD_DET 0 10 1 0 0 0 0 Set source of DSD processor to ASP Enable DSD playback Set DSD clock speed to 64•Fs Static DSD detection disabled Invalid DSD detection disabled 33 Configure DSD path Signal Control 3 DSD Processor Path Signal Control 3. 0x70006 0xC0 DSD_ZERODB DSD_HPF_EN Reserved SIGCTL_DSDEQPCM DSD_INV_A DSD_INV_B DSD_SWAP_CHAN DSD_COPY_CHAN 1 1 0 0 0 0 0 0 The SACD 0–dB reference level (50%modulation index) matches PCM 0-dB full scale. Enable HPF in DSD processor Function is disabled Function is disabled Function is disabled Function is disabled Function is disabled 34 Configure headphone output for 1.732 V rms 35 Configure Class H amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 1 11 1 0 Output signal determines voltage level High voltage mode enabled Using internal VCPFILT source. 36 Set HP output to full scale HP Output Control 1. 0x80000 0x30 HP_CLAMPA HP_CLAMPB OUT_FS HP_IN_EN Reserved 0 0 11 0 000 Set headphone output to full scale (1.732 V rms) 37 Headphone detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 11 0 0 0 10 0 HP detect enabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 38 Enable interrupts 39 Read Interrupt Status 1 register (0xF0000), Interrupt Status 2 register (0xF0001) and Interrupt Status 5 register (0xF0004) to clear sticky bits. 40 Enable headphone detect interrupts Interrupt Mask 1. 0xF0010 0x99 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK 1 0 0 1 1 0 0 1 DAC_OVFL_INT is don't care Enable HPDETECT_PLUG interrupt Enable HPDETECT_UNPLUG interrupt XTAL_READY_INT is don't care XTAL_ERROR_INT is don't care PLL_READY interrupt already enabled PLL_ERROR interrupt already enabled PDN_DONE_INT is don't care 41 Enable ASP interrupts Interrupt Mask 2. 0xF0011 0x07 ASP_OVFL_INT_MASK ASP_ERROR_INT_MASK ASP_LATE_INT_MASK ASP_EARLY_INT_MASK ASP_NOLRCK_INT_MASK Reserved 0 0 0 0 0 111 Enable ASP_OVFL interrupt Enable ASP_ERROR interrupt Enable ASP_LATE interrupt Enable ASP_EARLY interrupt Enable ASP_NOLRCK interrupt 42 Enable DSD and DoP interrupts Interrupt Mask 5. 0xF0014 0x01 DSD_STUCK_INT_MASK DSD_INVAL_A_INT_MASK DSD_INVAL_B_INT_MASK DSD_SILENCE_A_INT_MASK DSD_SILENCE_B_INT_MASK DSD_RATE_ERROR_INT_MASK DOP_MRK_DET_INT_MASK DOP_ON_INT_MASK 0 0 0 0 0 0 0 1 Enable DSD_STUCK interrupt Enable DSD_INVAL_A interrupt Enable DSD_INVAL_B interrupt Enable DSD_SILENCE_A interrupt Enable DSD_SILENCE_B interrupt Enable DSD_RATE_ERROR interrupt Enable DOP_MRK_DET interrupt Disable DOP_ON interrupt 43 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000). Example 5-13. DoP Playback with PLL (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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