CS43130 datasheet(27/137 Pages) CIRRUS

27 / 137 page

DS1073F1

CS43130

4.2 Analog Outputs

The CS43130 provides an analog output that is derived from the digital audio input ports. This section describes the

general flow of the analog outputs.

4.2.1

Analog Output Signal Flow

The CS43130 signal flow is shown in Fig. 4-1.

Figure 4-1. Analog Output Signal Flow

The CS43130 has 4 settings of full scale voltage, which are determined by OUT_FS[1:0]. The proper full scale voltage

must be set first, and the digital volume settings is used to control signal levels.

The CS43130 digital volume control allows independent control of the signal level in 1/2 dB increments from 0 dB

(0b0000 0000) to –127 dB (0b1111 1110) by using x_VOLUME_y (where "x" is either PCM or DSD; "y" is either A or B)

volume changes are implemented as dictated by PCM_SZC[1:0] and DSD_SZC in the signal control register (see

Section 7.4.3 and Section 7.5.5). If soft ramping is enabled, gain and attenuation changes are carried out by incrementally

changing the volume level in 1/8-dB steps, from the previous level to the new level. For PCM, when PCM_SZC[1:0] = 2,

the volume level changes at an approximate rate of 1 dB/ms. For DSD, when DSD_SZC = 1, the volume level also

changes at an approximate rate of 1 dB/ms during power up or when coming out of a mute state (DSD_MUTE_x = 1). Note

that when recovering from an error state caused by static DSD data (DSD_STUCK_INT = 1), the volume output will

resume at the level specified in DSD_VOLUME_x registers. Both channels can be inverted by setting the INV_A and INV_

B bits.

The CS43130 provides individual ramp-up control option (from the global soft ramp settings) for a specific scenario. The

PCM_RAMP_DOWN bit is for the scenario when the interpolation filter switches during PCM playback. Refer to the

The CS43130 can mute both channels simultaneously or independently. Also, it can auto-mute on both PCM stream and

DSD stream when mute pattern is identified (defined in PCM_AMUTE and DSD_AMUTE). Additional signal and mute

control options can be found in Section 7.4.3 and Section 7.5.5.

The CS43130 has an independent set of controls for the DSD processor path as shown in Fig. 4-1. The DSD processor

also offers the control bit SIGCTL_DSDEQPCM, which maps the PCM_x setting to DSD_x setting, once enabled. As a

result, some of the DSD_x register settings are ignored. The registers affected are DSD_VOL_BEQA, DSD_SZC, DSD_

Multibit



Modulator

Multibit



Modulator

Interpolation

Filter &

Volume

Control

Interpolation

Filter &

Volume

Control

DAC and

Filter

DAC and

Filter

–

HPINB

HPINA

HPOUTA

HPOUTB

DSD

Processor

DoP to

DSD

Engine

Audio

Source

HPREFB

HPREFA

DoP

DSD



HP_IN_EN p. 109

PDN_HP p. 97

DSD_EN p. 108

MIX_PCM_PREP p. 108

MIX_PCM_DSD p. 108

PCM_SZC p. 111

PCM_RAMP_DOWN p. 111

PCM_VOLUME_B p. 110

PCM_VOLUME_A p. 110

PCM_INV_A p. 111

PCM_INV_B p. 111

PCM_VOL_BEQA p. 111

PCM_AMUTE p. 111

PCM_AMUTEBEQA p. 111

PCM_MUTE_A p. 111

PCM_MUTE_B p. 111

FILTER_SLOW_FASTB

p. 110

PHCOMP_LOWLATB p. 110

HIGH_PASS p. 110

DEEMP_ON p. 110

NOS p. 110

DAC_OVFL_INT

p. 115

DSD_PRC_SRC p. 108

DSD_SPEED p. 108

STA_DSD_DET p. 108

INV_DSD_DET p. 108

DSD_VOLUME_B p. 106

DSD_VOLUME_A p. 107

DSD_INV_A p. 109

DSD_INV_B p. 109

DSD_VOL_BEQA p. 107

DSD_AMUTE p. 107

DSD_MUTE_A p. 107

OUT_FS p. 109

PDN_HP p. 97

DSD_MUTE_B p. 107

DSD_ZERODB p. 108

DSD_HPF_EN p. 109

OUT_FS p. 109

DSD_SZC p. 107

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