CS43130 datasheet(13/137 Pages) CIRRUS

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DS1073F1

CS43130

3 Characteristics and Specifications

Other characteristics

for HPOUTx

Interchannel gain mismatch (defined in Table 3-1)—

±0.1

—

Interchannel phase mismatch (defined in Table 3-1)—

±0.05

—

Output offset voltage: Mute (defined in Table 3-1)—

±0.5

±1

Gain drift (defined in Table 3-1)

—

±100

—

ppm/°C

Load resistance (RL)600

—



Load capacitance (CL)—

—

Turn-on time (defined in Table 3-1)—

—

Click/pop during PDN_HP enable or disable

A-weighted

—

–60

dBV

1.This table also applies to external VCP_FILT supply mode: CS43130 power up procedure is per description in Section 5.10.1; EXT_VCPFILT = 1;

VCP_FILT+ and VCP_FILT– comply to

Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN setting becomes don’t care.

2.One LSB of triangular PDF dither is added to PCM data.

3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table.

4.DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index.

5.The volume must be configured as indicated to achieve specified output characteristics.

6.Output test configuration. Symbolized component values are specified in the test conditions.

Table 3-5. Analog Output Characteristics (HV_EN = 0) 1

Test conditions (unless otherwise specified): Fig. 2-1 shows CS43130 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless

specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; HV_EN = 0; ASP_M/Sb = 1; typical, min/max performance

data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK

= 44.1-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); Volume = 0 dB; when testing

in DSD processor mode, DSD_ZERODB = 1

; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external

impedance on HPREFx.

PCM and DSD Processor Mode Parameter 2,3,4

Minimum

Typical

Maximum

Units

HPOUTx;

RL = 10 k

CL = 200 pF

OUT_FS = 10

Volume = 0 dB,5

unless otherwise

specified

Dynamic range

(defined in Table 3-1)

24-bit, 32-bit, DSD

16-bit

A-weighted

Unweighted

A-weighted

Unweighted

122

119

128

125

—

THD+N

(defined in Table 3-1)

24-bit, 32-bit, DSD

16-bit

0 dB

–20 dB

–60 dB

0 dB

–20 dB

–60 dB

—

–109

–95

–65

–94

–74

–34

–103

—

–59

–88

—

–28

Idle channel noise

(A-weighted)

(defined in Table 3-1)

24-bit, 32-bit, DSD

—

0.55

—

µV

Full-scale output voltage

3.76

3.96

4.16

Vpp

Interchannel isolation 6 (defined in Table 3-1)

217 Hz

1 kHz

20 kHz

—

110

—

Table 3-4. Analog Output Characteristics (HV_EN = 1) 1 (Cont.)

Test conditions (unless otherwise specified): Fig. 2-1 shows CS43130 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless

specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; HV_EN = 1; ASP_M/Sb = 1; typical, min/max performance

data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK

= 44.1-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); Volume = 0 dB; when testing

in DSD processor mode, DSD_ZERODB = 1

; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external

impedance on HPREFx.

PCM and DSD Processor Mode Parameter 2,3,4

Minimum

Typical

Maximum

Units

Test Load

HPOUTA

CLA

HPREFA

RLA

Measurement

Device

–

HPOUTB

HPREFB

CH1

CH2

CLB

RLB

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