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CS43130 Datasheet(PDF) 39 Page - Cirrus Logic |
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CS43130 Datasheet(HTML) 39 Page - Cirrus Logic |
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39 / 137 page ![]() DS1073F1 39 CS43130 4.7 Clock Output and Fractional-N PLL Figure 4-16. MCLK Source Switching A source to MCLK_INT, either the XTAL (or external MCLK), the PLL, or the RCO, must be provided as long as the CS43130 is operating; otherwise, the CS43130 enters a nonresponsive state, and I2C SDA signal can be held low. The only way to recover from this nonresponsive state is either through a reset or a POR event. Switching MCLK sources during DAC operation causes audible artifacts, but does not put the device in an unrecoverable state. In an MCLK source-switching event, the intended clock source must be present and ready before switching occurs. After POR or reset event, RCO is selected as default source of MCLK_INT. 4.6.1.1 Internal RC Oscillator As described in Section 4.6.1, the CS43130 includes an internal RC oscillator that can be used as a clock source for peripheral circuit such as control port or charge pump. 4.7 Clock Output and Fractional-N PLL The CS43130 clock output can be used as a master clock for other data-conversion or signal-processing components, which requires synchronous timing to the CS43130. The CLKOUT output is enabled by clearing PDN_CLKOUT. Figure 4-17. CLKOUT Source Selection Once enabled, CLKOUT is generated either from the internal crystal oscillator output (when used) or from the integrated fractional-N PLL; it can be selected by CLKOUT_SEL. CLKOUT_DIV can be used to set /2, /3, /4, or /8 to divide the selected clock source to targeted frequency. 4.7.1 Fractional-N PLL The CS43130 has an integrated fractional-N PLL to support the clocking requirements of various applications. This PLL can be enabled or disabled by clearing or setting PDN_PLL bit. The input reference clock for the PLL is signal on XTI/ MCLK pin (crystal-generated or external-feed). Internal PLL XTI/MCLK Internal MCLK CLKOUT ÷ RCO CLKOUT_SEL p. 100 PDN_PLL p. 97 MCLK_SRC_SEL p. 96 CLKOUT_DIV p. 100 MCLK_INT p. 96 XTI/MCLK PLL_OUT CLKOUT ÷ CLKOUT_DIV CLKOUT_SEL p. 100 |
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