CS43130 datasheet(44/137 Pages) CIRRUS

44 / 137 page

DS1073F1

CS43130

4.9 Audio Serial Port (ASP)

As shown in Fig. 4-20, the master-mode SCLK output for each serial port is derived from the internal MCLK. The SCLK

output can be configured to various frequencies to accommodate many sample rates, sample sizes, and channel counts.

The SCLK is output of a fractional divide from the internal MCLK input, where N is the numerator and M is the denominator.

Note: Depending on the chosen fractional divide configuration, the SCLK duty cycle can vary by one MCLK period.

Input and output SCLK polarity controls (xSP_SCPOL_IN and xSP_SCPOL_OUT) are also available. As shown in

Fig. 4-20, if Master Mode is used, both polarity controls affect the SCLK used by the serial port module. For example, both

polarity controls must be set to invert (xSP_SCPOL_IN = xSP_SCPOL_OUT = 1) to invert the SCLK output and output

data on the falling edge. In typical use cases, the values of xSP_SCPOL_IN equals xSP_SCPOL_OUT in each serial port.

See Fig. 4-23 for example waveforms showing the various settings of the SCLK polarity controls.

Likewise, input and output LRCK polarity controls (xSP_LCPOL_IN and xSP_LCPOL_OUT) are available. In Master

Mode, both LRCK polarity controls affect the LRCK used by the serial-port module as shown in Fig. 4-21. In typical-use

cases, the value of xSP_LCPOL_IN equals xSP_LCPOL_OUT in each serial port.

Figure 4-21. xSP LRCK Architecture

As shown in Fig. 4-22, xSP_LCPR determines the LRCK/FSYNC period, in units of SCLK periods. The LRCK period

effectively sets the length of the frame and the number of SCLK periods per Fs. Frame length may be programmed in

single SCLK period multiples from a minimum of 16 SCLK:Fs up to 1536 SCLK:Fs.

The LRCK-high width (xSP_LCHI) controls the number of SCLK periods for which the LRCK signal is held high during

each frame. Like the LRCK period, the LRCK-high width is programmable in single SCLK periods, from a minimum of one

period to a maximum of the LRCK period minus one (and an absolute maximum of 768 SCLK periods). That is, LRCK-high

width must be less than the LRCK period.

Figure 4-22. xSP LRCK Period, High Width

LRCK to

Serial Port

ASP_LRCK/FSYNC

PER

OUT

LR GEN

From SCLK

x_M/S = 1 (master) &

PDN_x = 0 (enabled )

5050

DELAY

ASP_5050 p. 102/XSP_5050 p. 104

ASP_FSD p. 102/XSP_FSD p. 105

ASP_LCPOL_IN p. 102/

XSP_LCPOL_IN p. 104

ASP_M/SB p. 102/

XSP_M/SB p. 104

ASP_LCPOL_OUT p. 102/

XSP_LCPOL_OUT p. 104

ASP_LCHI_LSB p. 101/XSP_LCHI_LSB p. 103

ASP_LCHI_MSB p. 101/XSP_LCHI_MSB p. 103

ASP_LCPR_LSB p. 101/XSP_LCPR_LSB p. 104

ASP_LCPR_MSB p. 101/XSP_LCPR_MSB p. 104

SCLK

LRCK

Falling

Edge

Rising

Edge

xSP_LCPR

xSP_LCHI

...

CS43130 Datasheet(PDF) 44 Page - Cirrus Logic

CS43130 Datasheet(HTML) 44 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL