CS43130 datasheet(41/137 Pages) CIRRUS

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DS1073F1

CS43130

4.8 Filtering Options

Note that in Table 4-4 and Table 4-5:

• The PLL_OUT_DIV value must be even.

• PLL_OUT frequencies are at 22.5792 or 24.576 MHz. CLKOUT frequencies can be obtained by configuring the

CLKOUT_DIV value:

• PLL_ERROR_INT constantly monitors the PLL error status after PLL_START is set, assuming the PLL reference

input is stable and accurate.

4.7.2.1 Powering Up the PLLs

To power up the PLL, follow the following default sequence:

1. Enable the PLL by clearing PDN_PLL.

2. Configure PLL_REF_PREDIV.

3. Configure PLL_OUT_DIV.

4. Configure the three fractional factor registers, PLL_DIV_FRAC.

5. Set the integer factor, PLL_DIV_INT, to the desired value.

6. Configure PLL_MODE and PLL_CAL_RATIO.

7. After properly unmasked (clearing PLL_READY_INT_MASK and PLL_ERROR_INT_MASK), PLL_READY_INT,

and PLL_ERROR_INT are used to monitor if PLL has been successfully started.

8. Turn on the PLL by setting PLL_START.

4.7.2.2 Powering Down the PLL

1. Clear PLL_START to stop the PLL operation.

2. For further power saving, set PDN_PLL to disable the PLL block.

4.8 Filtering Options

To accommodate the increasingly complex requirements of digital audio systems, the CS43130 incorporates selectable

filters in different playback modes. Note that when switching between filter options, the CS43130 headphone needs to be

powered down in accordance with the sequence specified in Section 5.7.1 first before applying any filter changes. After

the filter is changed, for audio playback, the CS43130 headphone must be powered up.

For PCM/TDM mode, the following interpolation filtering options can be selected:

• Fast roll-off and slow roll-off interpolation filter options.

• In each option above, both low-latency and normal phase-compensation filtering options can be used.

• Nonoversampling (NOS) mode is provided, which minimizes the internal digital processing. Once NOS mode is set,

the settings on the above two options are ignored.

19.200

0x3

0x49

0x80 0000

0x08

22.5792

151

0x3

0x50

0x00 0000

0x08

24.576

164

13.000

0x2

0x45

0x79 7680

0x0A

22.5792

111

40x2

0x3C

0x7E A940

0x08

24.576

121

26.000

0x3

0x45

0x79 7680

0x0A

22.5792

111

0x3

0x3C

0x7E A940

0x08

24.576

121

PLL_OUT

CLKOUT_DIV (2)

CLKOUT_DIV (3)

CLKOUT_DIV (4)

CLKOUT_DIV (8)

22.5792 MHz

11.2896 MHz

7.5264 MHz

5.6448 MHz

2.8224 MHz

24.576 MHz

12.288 MHz

8.192 MHz

6.144 MHz

4.096 MHz

Table 4-5. PLL Configuration for Typical Use Case (XIN/MCLK as the PLL Reference) (Cont.)

XIN/MCLK

(MHz)

PLL_REF_PREDIV

(Divide-by Value)

PLL_REF_PREDIV

(Setting)

PLL_DIV_INT PLL_DIV_FRAC PLL_OUT_DIV

PLL_

MODE

PLL_OUT

(MHz)

PLL_CAL_

RATIO

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