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CS43130 Datasheet(PDF) 72 Page - Cirrus Logic |
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CS43130 Datasheet(HTML) 72 Page - Cirrus Logic |
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72 / 137 page  72 DS1073F1 CS43130 5.10 Example Sequences 5.10.4 Analog-In Startup Ex. 5-14 shows an example sequence of starting up the CS43130 in analog passthrough mode. 5.10.5 Switching from Analog-In to PCM Playback Ex. 5-15 assumes that: • The CS43130 is powered up, out of reset, and is currently operating in analog passthrough mode as in Ex. 5-14. • The ASP and PCM interfaces are not yet configured. • CS43130 XTI/XTO is connected to a 22.5792-MHz crystal. • ASP interface is slave. 44 Set MCLK source and frequency System Clocking Control. 0x10006 0x05 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 1 01 MCLK Frequency is set to 22.5792 MHz MCLK Source is set to PLL 45 Wait for at least 150 µs. 46 Enable ASP clocks Pad Interface Configuration. 0x1000D 0x02 Reserved XSP_3ST ASP_3ST 0000 00 1 0 XSP Interface status is don't care (set to default) Enable serial clocks in Master Mode 47 Power up HP Refer to Ex. 5-10 for DSD power-up sequence. Note that in Step 2 of Ex. 5-10, HH = BF for DoP on ASP interface. Skip Step 1 of Ex. 5-10 (completed in Step 3 above). Example 5-14. Start Up to Analog-In STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 1 Apply all relevant power supplies, then assert RESET. 2 Wait for 1.5 ms. MCLK Source is set to RCO by default. 3 Enable Headphone detect. See Section 5.10.8 “Headphone Detection” 4 Enable HPINx path. See See Section 5.6.1 “HPINx Alternate Headphone Path Enable Sequence” Example 5-15. Switching from Analog-In to PCM Playback STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION 1 Configure XTAL driver. 2 Configure XTAL bias current strength (assuming River Crystal at 22.5792 MHz) Crystal Setting. 0x20052 0x04 Reserved XTAL_IBIAS 0000 0 100 Bias current set to 12.5 µA 3 Read Interrupt Status 1 register (0xF0000) to clear sticky bits. 4 Enable XTAL interrupts Interrupt Mask 1. 0xF0010 data(0xF0010) AND 0xE7 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK x x x 0 0 x x x Enable XTAL_READY interrupt Enable XTAL_ERROR interrupt 5 Start XTAL Power Down Control. 0x20000 data (0x20000) AND 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved x x x x 0 x x 0 Power up XTAL driver 6 Apply PCM power-up initialization. Refer to Ex. 5-7 7 Configure ASP interface. Sample rate set to 44.1 kHz. ASP is slave to incoming clock. 8 Set ASP sample rate Serial Port Sample Rate. 0x1000B 0x01 Reserved ASP_SPRATE 0000 0001 Set sample rate to 44.1 kHz Example 5-13. DoP Playback with PLL (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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