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LM9800 Datasheet(PDF) 22 Page - National Semiconductor (TI) |
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LM9800 Datasheet(HTML) 22 Page - National Semiconductor (TI) |
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22 / 34 page ![]() Configuration Register t MCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (t MCLK = 50ns). (Continued) TABLE 2. Configuration Register Parameters (Continued) Parameter Control Bits Result VGA State for Pixel “a” VGA a 0 VGA bypassed 1 VGA on Offset DAC Sign VOS1 VOS1 VOS0 Offset (LSB) 1000 0 1001 +1 1010 +2 1011 +3 1100 +4 1101 +5 1110 +6 1111 +7 0000 0 0001 −1 0010 −2 0011 −3 0100 −4 0101 −5 0110 −6 0111 −7 Block Diagram of LM9800-Based System DS012498-33 Note: Power supplies and bypass capacitors not shown for clarity. FIGURE 27. LM9800 System Block Diagram www.national.com 22 |
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