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LM9800 Datasheet(PDF) 18 Page - National Semiconductor (TI) |
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LM9800 Datasheet(HTML) 18 Page - National Semiconductor (TI) |
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18 / 34 page ![]() Configuration Register t MCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (t MCLK = 50ns). TABLE 1. Configuration Register Address Table A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 000 Standard RS Pulse Width RS Pulse Polarity RS Pulse Position (Minimum Value is 1) Mode or Even/Odd Mode MODE RSW1 RSW0 RSPOL RSPOS3 RSPOS2 RSPOS1 RSPOS0 001 Sample Reference Position Sample Signal Position SR3 SR2 SR1 SR0 SS3 SS2 SS1 SS0 010 φ1 φ2RS TR TR Pulse Width TR– φ1TR Enable Enable Enable Enable Guardband Polarity φ1EN φ2EN RSEN TREN TRW1 TRW0 TRGRD TRPOL 011 Dummy Pixels (Minimum Value is 1) BLS7 BLS6 BLS5 BLS4 BLS3 BLS2 BLS1 BLS0 100 Optical Black Pixels (Minimum Value is 1) BLL7 BLL6 BLL5 BLL4 BLL3 BLL2 BLL1 BLL0 101 PGA Gain Coefficient 0 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 110 PGA Gain Test Power- Offset VGA VGA State VGA State VGA State Source Mode down Add On/Off Pixel c Pixel b Pixel a PGASRC 0 PD OFFADD VGA G3 G2 G1 111 Offset DAC Offset DAC Offset DAC Offset DAC Test Modes Sign MSB LSB ODSIGN VOS2 VOS1 VOS0 0 0 0 0 www.national.com 18 |
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