LM9800 datasheet(6/34 Pages) NSC

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AC Electrical Characteristics, MCLK Dependent

The following specifications apply for AGND = DGND = DGND

(I/O) = 0V, VA = VD = VD(I/O) = +5.0 VDC, REF IN = +1.225

DC,fMCLK = 20MHz, tMCLK = 1/fMCLK,tr = tf = 5ns, Rs = 25Ω,CL (databus loading) = 50 pF/pin. Refer to Table 2 : Configu-

ration Register Parameters for limits labelled C.R. Boldface limits apply for T

A = TJ = TMIN to TMAX; all other limits TA =

J = 25˚C.

Symbol

Parameter

Conditions

Typical

Limits

Units

(Note 9)

(Note 10)

(Limits)

START

MCLK to first

φ1 high

50ns

MCLK

tφ

φ1, φ2 Clock Period

Standard CCD Mode

400ns

MCLK

Even/Odd CCD Mode

800ns

MCLK

TRWIDTH

Transfer Pulse (TR) Width

C.R.

µs

GUARD

φ1 to TR, TR to φ1 Guardband

C.R.

RSWIDTH

Reset Pulse (RS) Width

C.R.

Falling Edge of

φ1 to RS

Standard CCD Mode

C.R.

Either Edge of

φ1 to RS

Even/Odd CCD Mode

S/HREF

Falling Edge of

φ1 to Ref. Sample

Standard CCD Mode

C.R.

Either Edge of

φ1 to Ref. Sample

Even/Odd CCD Mode

S/HSIG

Falling Edge of

φ1 to Sig. Sample

Standard CCD Mode

C.R.

Either Edge of

φ1 to Sig. Sample

Even/Odd CCD Mode

S/HWIDTH

Sample Pulse Width

50ns

MCLK

(Acquisition Time)

SYNCLOW

SYNC Low Between Lines

100ns

MCLK (min)

SYNC Setup of

φ1 to end line

MCLK (max)

CCLKWIDTH

CCLK Pulse Width

250ns

MCLK

DATAVALID

Data Valid Time from EOC Low

300

ns (min)

EOCWIDTH

EOC Pulse Width

250ns

MCLK

φ1 and φ2 Frequency

Standard CCD Mode

2.5MHz

MCLK/8

Even/Odd CCD Mode

1.25MHz

MCLK/16

φ1 and φ2 Duty Cycle

Electrical Characteristics (Notes)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test condi-

tions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = DGND(I/O) = 0V, unless otherwise specified.

Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN >VA or VD), the current at that pin should be limited to 25 mA. The

50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to

two.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum

allowable power dissipation at any temperature is PD = (TJmax–TA)/θJA.TJmax = 150˚C for this device. The typical thermal resistance θJA of this part when board

mounted is 52˚C/W for the V52A PLCC package.

Note 5: Human body model, 100 pF capacitor discharged through a 1.5

Ω resistor.

Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semi-

conductor Linear Data Book for other methods of soldering surface mount devices.

Note 7: A Zener diode clamps the OS analog input to AGND as shown below. This input protection, in combination with the external clamp capacitor and the output

impedance of the CCD, prevents damage to the LM9800 from transients during power-up.

Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin.

Note 9: Typicals are at TJ = TA = 25˚C, fMCLK = 20MHz, and represent most likely parametric norm.

Note 10: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

DS012498-4

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