LM9800 datasheet(23/34 Pages) NSC

23 / 34 page

Applications Information

1.0 THEORY OF OPERATION

The LM9800 removes errors from and digitizes a linear CCD

pixel stream, while providing all the necessary clock signals

to drive the CCD. Offset and gain errors are removed at the

pixel rate, for individual pixels. Offset errors are removed

through correlated double sampling (CDS). Gain errors

(which may come from any combination of PRNU, uneven il-

lumination, cos

4 effect, RGB filter mismatch, etc.) are re-

moved through the use of a 7-bit PGA in front of the ADC.

1.1 The Analog Signal Path

(See Block Diagram)

The analog output signal from the CCD is connected to the

OS Input of the LM9800 through a 0.001µF (typical, see sec-

tion 4.2,

Clamp Capacitor Selection ) DC blocking capacitor.

During the CCD’s optical black pixel segment at the begin-

ning of every line, this input is clamped to the REF OUT

MID

voltage (approximately 2.45V). This DC restore operation

fixes the reference level of the CCD pixel stream at REF

OUT

MID.

The signal is then buffered and fed to a voltage-controlled

VGA (variable gain amplifier). The VGA can be used to com-

pensate for peak white CCD outputs less than the 1.225V

full-scale required by the LM9800 for maximum dynamic

range. It can also be used to increase the gain of the Blue

signal in a sequential-output RGB CCD, since the VGA can

be switched in and out of the circuit at the pixel rate. When

used with parallel output CCDs the VGA can be used (in con-

junction with an external multiplexer) to fine-tune the ampli-

tude of the red, green, and blue signals. For a detailed expla-

nation of the VGA, see section 4.3,

GAIN (VGA) Input.

The output of the VGA goes into the CDS (Correlated Double

Sampling) stage, consisting of two sample/hold amplifiers:

S/H Ref (Reference) and S/H Signal. The Reference Level is

sampled and held by the S/H Ref circuit and the active pixel

data is sampled and held by the S/H Signal circuit. The out-

put of S/H Ref is subtracted from the S/H Signal output and

amplified by 2. The full-scale signal range at this point is ap-

proximately 2.45Vp-p. CDS reduces or eliminates many

sources of noise, including reset noise, flicker noise, and

both high and low frequency pixel-to-pixel offset variation.

For more information on the CDS stage, see section 4.5,

Correlated Double Sampler (CDS) .

At this point an offset voltage can be injected by the 4-bit Off-

set DAC. This voltage is designed to compensate for any

small fixed DC offset introduced by the CDS S/Hs and the x2

amplifier. The LSB size of the DAC is approximately 1 LSB

(10mV).The adjustment range is ±7 LSBs. For a detailed ex-

planation of the Offset DAC, see section 4.6.

The next stage is the PGA. This is a programmable gain am-

plifier that changes the gain

at the pixel rate to correct for

gain errors due to PRNU, uneven illumination (such as cos

effect), RGB filter mismatch, etc. The gain adjustment range

is 0 to 6 dB (x1 to x2) with 7 bits of resolution. The gain data

(correction coefficients) is provided on the CD0–CD6 bus.

The gain may also be fixed at any value between 0 dB and

6 dB with the PGA Gain Coefficient configuration register.

For further information on the PGA, see section 4.7.

An approximately 1 LSB (10mV) offset can be added at the

output of the PGA stage if necessary to ensure that the offset

is zero or positive. This eliminates the possibility of a nega-

tive offset clipping the darkest output pixels. For more infor-

mation on the Offset Add Bit, see section 4.8.

Finally, the output of the PGA is digitized by the ADC and

made available on the DD0–DD7 bus. For a detailed expla-

nation of the ADC, see section 4.9.

Three reference voltages are used throughout the signal

path: the externally supplied REF IN (1.225V), and the inter-

nally generated REF OUT

MID

(2.45V) and REF OUT

(3.675V).

1.2 The CCD Clocking Signals

To maximize the flexibility of the LM9800, the CCD’s

φ1, φ2,

RS, and TR pulses are internally generated, with a wide

range of options, compatible with most commercial linear

CCDs. In most cases, these output signals can drive most

CCD clock inputs directly, with only series resistors (for slew

rate control) between the LM9800’s outputs and the CCD

clock inputs.

1.3 The Digital Interface

There are three main sections to the digital interface of the

LM9800: a serial interface to the Configuration Register,

where all device programming is done, a 7 bit-wide input

databus for gain correction coefficients with a synchronous

clock output, and an 8-bit output databus for the final pixel

output data with a synchronous EOC output signal and a RD

input. Please note that CS affects only the serial I/O–it has

no effect on the output databus, input coefficient bus, or any

other section of the LM9800.

2.0 DIGITAL INTERFACE

2.1 Reading and Writing to the Configuration Register

Communication with the Configuration Register is done

through a standard MICROWIRE™ serial interface. This in-

terface is compatible with the Motorola SPI standard and is

simple enough to easily be implemented in custom hardware

if needed.

The serial interface timing is shown in

Figures 14, 15, 16, 17

and

Figures 19, 20, 21, 22. The SYNC pin must be pulled

high to read or write to the configuration register. Taking

SYNC high resets the internal serial counters. Data is sent

serially, LSB first. Input data is latched on the rising edge of

SCLK, and output data changes on the falling edge of SCLK.

CS must be low to enable serial I/O.

If SCLK is only clocked when sending or receiving data from

the LM9800, and held low at all other times, then CS can be

tied low permanently as shown in

Figures 14, 15, 16, 17.If

SCLK is continuous, then CS is used to determine the begin-

ning and the end of a serial byte or word (see

Figures 19, 20,

21, 22). Note that CS must make its high-to-low and

low-to-high transitions when SCLK is low, otherwise the in-

ternal bit counter may receive an erroneous pulse, causing

an error in the write or read operation.

Data may be transmitted and received in two 8-bit bytes

(typical with microcontroller interfaces) or one 16-bit word

(for custom serial controllers).

The Configuration Register is programmed by sending a

control byte to the serial port. This byte indicates whether

this is a read or a write operation, and gives the 3-bit address

of the register bank to be read from or written to. If this is a

read operation, the next 8 SCLKs will output the data at the

requested location on the SDO pin. If this is a write opera-

tion, the data to be sent to the specified location should be

clocked in on the SDI input during the next 8 SCLKs. Data is

sent and received using the LSB (Least Significant Bit) first

format.

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