Note 11: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function

of the ADC.

tion, optics, etc.) that the LM9800 can correct for using its internal PGA.

Note 13: Reference voltages below 1.19V may decrease SNR. Reference voltages above 1.26V may cause clipping errors inside the LM9800. The

LM4041EIM3-1.2 (SOT-23 package) or the LM4041EIZ-1.2 (TO-92 package) bandgap voltage references are recommended for this application.

Typical Performance Characteristics

Pin Descriptions

CCD Driver Signals

φ1

Digital Output. CCD clock signal, phase

1.

φ2

Digital Output. CCD clock signal, phase

2.

RS

Digital Output. Reset pulse for the CCD.

TR

Digital Output. Transfer pulse for the

CCD.

Analog I/O

OS

Analog Input. This is the OS (Output

Signal) from the CCD. The maximum

peak signal that can be accurately

digitized is equal to the voltage at REF

IN, typically 1.225V.

GAIN

Analog Input. The voltage on this pin

determines the gain of the VGA when

the VGA is enabled. This input should

be bypassed to AGND using a 0.1 µF

monolithic capacitor.

REF IN

Analog Inputs. These two pins are the

system reference voltage inputs and

should be tied together to a 1.225V

voltage source and bypassed to AGND

with a 0.1 µF monolithic capacitor.

REF OUT

HI

Analog Output. This reference voltage is

developed internally by the LM9800, and

is equal to 3 times REF IN. It should be

bypassed to AGND with a 0.1 µF

monolithic capacitor.

REF OUT

MID

Analog Output. This reference voltage is

developed internally by the LM9800, and

is equal to 2 times REF IN. It should be

bypassed to AGND using a 0.1 µF

monolithic capacitor. This pin can

source up to 250 µA when used to

power a voltage divider for setting the

voltage at the GAIN input.

I

SET

Analog Input. This input is used to set

internal bias currents inside the LM9800.

It should be connected to V

75 k

Ω resistor.

DS012498-5

VGA Gain vs Voltage on GAIN Input

DS012498-48

φ1, φ2, RS, TR Rise and Fall Times Through a

Series Resistance vs. Load Capacitance

DS012498-49

7

www.national.com