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LM9800 Datasheet(PDF) 19 Page - National Semiconductor (TI) |
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LM9800 Datasheet(HTML) 19 Page - National Semiconductor (TI) |
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19 / 34 page ![]() Configuration Register t MCLK = 1/fMCLK = 1 MCLK period. Examples given in parenthesis are for fMCLK = 20MHz (t MCLK = 50ns). (Continued) TABLE 2. Configuration Register Parameters Parameter Control Bits Result MODE MODE 0 Standard CCD ( φ frequency = f MCLK/8) 1 Even/Odd CCD ( φ frequency = f MCLK/16) RS Pulse Width (t RSWIDTH) RS1 RS0 00 1t MCLK (50ns) 01 2t MCLK (100ns) 10 3t MCLK (150ns) 11 4t MCLK (200ns) RS Pulse Polarity RSPOL 0 RS 1 RS RS Pulse Position (t RS) Note: Minimum Value is 1 RSPOS3 RSPOS2 RSPOS1 RSPOS0 0000 Not Valid 0001 0.5t MCLK (25 ns) 0010 1.0t MCLK (50ns) 0011 1.5t MCLK (75ns) 0100 2.0t MCLK (100ns) 0101 2.5t MCLK (125ns) 0110 3.0t MCLK (150ns) 0111 3.5t MCLK (175ns) 1000 4.0t MCLK (200ns) 1001 4.5t MCLK (225ns) 1010 5.0t MCLK (250ns) 1011 5.5t MCLK (275ns) 1100 6.0t MCLK (300 ns) 1101 6.5t MCLK (325 ns) 1110 7.0t MCLK (350 ns) 1111 7.5t MCLK (375 ns) Sample Reference Position (t S/HREF) SR3 SR2 SR1 SR0 0000 0.0t MCLK (0 ns) 0001 0.5t MCLK (25 ns) 0010 1.0t MCLK (50 ns) 0011 1.5t MCLK (75 ns) 0100 2.0t MCLK (100 ns) 0101 2.5t MCLK (125 ns) 0110 3.0t MCLK (150 ns) 0111 3.5t MCLK (175 ns) 1000 4.0t MCLK (200 ns) 1001 4.5t MCLK (225 ns) 1010 5.0t MCLK (250 ns) 1011 5.5t MCLK (275 ns) 1100 6.0t MCLK (300 ns) 1101 6.5t MCLK (325 ns) 1110 7.0t MCLK (350 ns) 1111 7.5t MCLK (375 ns) 19 www.national.com |
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