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AD9230 Datasheet(PDF) 23 Page - Analog Devices |
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AD9230 Datasheet(HTML) 23 Page - Analog Devices |
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23 / 33 page  AD9230 Rev. 0 | Page 22 of 32 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9230 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ pin and CLK− pin via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 55 shows one preferred method for clocking the AD9230. The low jitter clock source is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9230 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9230 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1µF 0.1µF 0.1µF 0.1µF CLOCK INPUT 50Ω 100Ω CLK– CLK+ ADC AD9230 MINI-CIRCUITS ADT1–1WT, 1:1Z XFMR SCHOTTKY DIODES: HSM2812 Figure 55. Transformer-Coupled Differential Clock If a low jitter clock is available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 56. The AD9510/AD9511/AD9512/AD9513/ AD9514/AD9515 family of clock drivers offers excellent jitter performance. 100Ω 0.1µF 0.1µF 0.1µF 0.1µF 240Ω 240Ω AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 50Ω1 50Ω1 CLK CLK 150Ω RESISTORS ARE OPTIONAL. CLK– CLK+ ADC AD9230 PECL DRIVER CLOCK INPUT CLOCK INPUT Figure 56. Differential PECL Sample Clock CLOCK INPUT CLOCK INPUT 100Ω 0.1µF 0.1µF 0.1µF 0.1µF 50Ω1 LVDS DRIVER 50Ω1 CLK CLK 150Ω RESISTORS ARE OPTIONAL. CLK– CLK+ ADC AD9230 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 Figure 57. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 58). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.3 V, making the selection of the drive logic voltage very flexible. 0.1µF 0.1µF 0.1µF 39kΩ CMOS DRIVER 50Ω1 OPTIONAL 100Ω 0.1µF CLK CLK 150Ω RESISTOR IS OPTIONAL. CLK– CLK+ ADC AD9230 AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLOCK INPUT Figure 58. Single-Ended 1.8 V CMOS Sample Clock 0.1µF 0.1µF 0.1µF CMOS DRIVER CLK CLK 150Ω RESISTOR IS OPTIONAL. 0.1µF CLK– CLK+ AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 ADC AD9230 CLOCK INPUT 50Ω1 OPTIONAL 100Ω Figure 59. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9230 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9230. When the DCS is on, noise and distortion perfor- mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the AD9230 Configuration Using the SPI section for more details on using this feature. The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. |
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