COP404C datasheet(8/18 Pages) NSC

8 / 18 page

Functional Description (Continued)

chip will stop as soon as CKI is high and CKOH output will

stay high to keep the chip stopped if the external driver

returns to high impedance state

Once in the HALT mode the internal circuitry does not re-

ceive any clock signal and is therefore frozen in the exact

state it was in when halted All information is retained until

continuing

The chip may be awakened by one of two different meth-

ods

Continue function by forcing CKOH low the system

clock will be re-enabled and the circuit will continue to

operate from the point where it was stopped CKOH

will stay low

Restart by forcing the RESET pin low (see Initializa-

tion)

The HALT mode is the minimum power dissipation state

Note if the user has selected dual-clock (DUAL pin tied to

Ground) AND is forcing an external clock on D0 pin

AND the COP404C is running from the D0 clock the

HALT mode - either hardware or software - will NOT

be entered Thus the user should switch to the CKI

clock to HALT Alternatively the user may stop the D0

clock to minimize power

Oscillator Options

There are two basic clock oscillator configurations available

as shown by

Figure 9

CKI oscillator CKI is configured as a LSTTL compati-

ble input external clock signal The external frequency

is divided by 4 to give the instruction cycle time

Dual oscillator By tying DUAL pin to Ground pin D0 is

now a single pin RC controlled Schmitt trigger oscilla-

tor input The user may software select between the

D0 oscillator (the instruction cycle time equals the D0

oscillation frequency divided by 4) by setting the D0

latch high or the CKI oscillator by resetting D0 latch

low

Note that even in dual clock mode the counter if used

as a time-base counter is always connected to the CKI

oscillator

For example the user may connect up to a 1 MHz RC

circuit to D0 for faster processing and a 32 kHz exter-

nal clock to CKI for minimum current drain and time

keeping

Note CTMA instruction is not allowed when the chip is run-

ning from D0 clock

Figures 10a and 10b show the timer and clock diagrams

with and without Dual-Clock

TLDD5530 – 9

Cycle

Time

VCC

15k

82 pF

4b9 ms

45V

30k

82 pF

8b16 ms

45V

60k

100 pF

16b32 ms

24b45V

Note

15ksRs150k

50 pFsCs150 pF

FIGURE 9 Dual-Oscillator Component Values

TLDD5530 – 10

FIGURE 8 HALT Mode

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