COP404C datasheet(10/18 Pages) NSC

10 / 18 page

External Memory Interface

The COP404C is designed for use with an external Program

Memory

This memory may be implemented using any devices having

the following characteristics

1 random addressing

2 LSTTL or CMOS-compatible TRI-STATE outputs

3 LSTTL or CMOS-compatible inputs

4 access timee1 0 ms max

Typically these requirements are met using bipolar PROMs

or MOSCMOS PROMs EPROMs or E2PROMs

During operation the address of the next instruction is sent

out on A10 A9 A8 and IP7 through IP0 during the time that

ADDATA is high (logic ‘‘1’’eaddress mode) Address data

on the IP lines is stored into an external latch on the high-to-

low transition of the ADDATA line A10 A9 and A8 are

dedicated address outputs and do not need to be latched

When ADDATA is low (logic ‘‘0’’edata mode) the output

of the memory is gated onto IP7 through IP0 forming the

input bus Note that ADDATA output has a period of one

instruction time a duty cycle of approximately 50% and

specifies whether the IP lines are used for address output or

data input A simplified block diagram of the external memo-

ry interface is shown in

Figure 11

TLDD5530 – 13

FIGURE 11 External Memory Interface to COP404C

COP404C Instruction Set

Table II is a symbol table providing internal architecture in-

struction operand and operation symbols used in the in-

struction set table

Table III provides the mnemonic operand machine code

data flow skip conditions and description of each instruc-

tion

Table II Instruction Set Table Symbols

Symbol

Definition

Internal Architecture Symbols

4-bit Accumulator

7-bit RAM address register

Upper 3 bits of B (register address)

Lower 4 bits of B (digit address)

1-bit Carry register

4-bit Data output port

4-bit Enable register

4-bit General purpose IO port

two 1-bit (IN0 and IN3) latches

4-bit input port

8-bit TRI-STATE IO port

4-bit contents of RAM addressed by B

11-bit ROM address program counter

8-bit latch for L port

11-bit Subroutine Save Register A

11-bit Subroutine Save Register B

11-bit Subroutine Save Register C

SIO

4-bit Shift register and counter

Logic-controlled clock output

SKL

1-bit latch for SK output

8-bit timer

Instruction operand symbols

4-bit operand field 0 – 15 binary (RAM digit select)

3-bit operand field 0 – 7 binary (RAM register select)

11-bit operand field 0 – 2047

4-bit operand field 0 – 15 (immediate data)

RAM(x) RAM addressed by variable x

ROM(x) ROM addressed by variable x

Operational Symbols

Plus

Minus

– l

Replaces

– l

is exchanged with

Is equal to

one’s complement of A

exclusive-or

range of values

COP404C Datasheet(PDF) 10 Page - National Semiconductor (TI)

COP404C Datasheet(HTML) 10 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL