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COP404C Datasheet(PDF) 12 Page - National Semiconductor (TI) |
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COP404C Datasheet(HTML) 12 Page - National Semiconductor (TI) |
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12 / 18 page  Instruction Set (Continued) TABLE III COP404C Instruction Set (Continued) Machine Mnemonic Operand Hex Language Data Flow Skip Description Code Code Conditions (Binary) SMB 0 4D l0100l1101l 1 x RAM(B)0 None Set RAM Bit 147 l0100l0111l 1 x RAM(B)1 246 l0100l0110l 1 x RAM(B)2 34B l0100l1011l 1 x RAM(B)3 STII y 7b l0111l y l y x RAM(B) None Store Memory Immediate Bd a 1 x Bd and Increment Bd Xr b 6 l00l r l0110l RAM(B) A None Exchange RAM with A (re03) Br Z r x Br Exclusive-OR Br with r XAD rd 23 l0010l0011l RAM(rd) A None Exchange A with RAM l1l r l d l pointed to directly by rd XDS r b 7 l00l r l0111l RAM(B) A Bd Exchange RAM with A (re03) Bdb1 x Bd decrements and Decrement Bd Br Z r x Br past 0 Exclusive-OR Br with r XIS r b 4 l00l r l0100l RAM(B) A Bd Exchange RAM with A (re03) Bda1 x Bd increments and Increment Bd Br Z r x Br past 15 Exclusive-OR Br with r REGISTER REFERENCE INSTRUCTIONS CAB 50 l0101l0000l A x Bd None Copy A to Bd CBA 4E l0100l1110l Bd x A None Copy Bd to A LBI rd l00l r l(d-1)l rd x B Skip until Load B Immediate with rd (re03 not a LBI (Note 5) de0915) or 33 l0011l0011l l1l r l d l (any r any d) LEI y 33 l0011l0011l y x EN None Load EN Immediate (Note 6) 6b l0110l y l XABR 12 l0001l0010l A Br None Exchange A with Br (Note 7) TEST INSTRUCTIONS SKC 20 l0010l0000l Ce‘‘1’’ Skip if C is True SKE 21 l0010l0001l AeRAM(B) Skip if A Equals RAM SKGZ 33 l0011l0011l G30e0 Skip if G is Zero 21 l0010l0001l (all 4 bits) SKGBZ 33 l0011l0011l 1st byte Skip if G Bit is Zero 001 l0000l0001l G0e0 111 l0001l0001l 2nd byte G1e0 203 l0000l0011l G2e0 313 l0001l0011l G3e0 SKMBZ 0 01 l0000l0001l RAM(B)0e0 Skip if RAM Bit is Zero 111 l0001l0001l RAM(B)1e0 203 l0000l0011l RAM(B)2e0 313 l0001l0011l RAM(B)3e0 SKT 41 l0100l0001l A time-base Skip on Timer counter (Note 2) carry has occured since last test 12 |
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