TABLE III COP404C Instruction Set

(Continued)

Machine

Mnemonic

Operand

Hex

Language

Data Flow

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Description

Code

Code

Conditions

(Binary)

INPUTOUTPUT INSTRUCTIONS

ING

33

G

None

Input G Ports to A

2A

ININ

33

IN

None

Input IN Inputs to A

28

INIL

33

None

Input IL Latches to A

29

(Note 2)

INL

33

None

Input L Ports to RAMA

2E

OBD

33

Bd

None

Output Bd to D Outputs

3E

OGI

y

33

y

None

Output to G Ports

Immediate

OMG

33

RAM(B)

None

Output RAM to G Ports

3A

XAS

4F

A

SIO C

None

Exchange A with SIO

(Note 2)

Note 1

All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (eg Br and Bd are explicitly defined) Bits are numbered O to N where

Note 2

For additional information on the operation of the XAS JID LQID INIL and SKT instructions see below

Note 3

The JP instruction allows a jump while in subroutine pages 2 or 3 to any ROM location within the two-page boundary of pages 2 or 3 The JP instruction

otherwise permits a jump to a ROM location within the current 64-word page JP may not jump to the last word of a page

Note 4

A JSRP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P) A JSRP may not be used when in pages 2 or 3 JSRP

may not jump to the last word in page 2

Note 5

Note 6

Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN where a ‘‘1’’ or ‘‘0’’ in each bit of EN corresponds

with the selection or deselection of a particular function associated with each bit (See Functional Description EN Register)

Note 7

Br (0

Br (00

Description of Selected Instructions

XAS INSTRUCTION

XAS (Exchange A with SIO) copies C to the SKL latch and

exchanges the accumulator with the 4-bit contents of the

SIO register The contents of SIO will contain serial-inseri-

al-out shift register or binary counter data depending on the

value of the EN register If SIO is selected as a shift register

an XAS instruction can be performed once every 4 instruc-

tion cycles to effect a continuous data stream

LQID INSTRUCTION

LQID (Load Q Indirect) loads the 8-bit Q register with the

contents of ROM pointed to by the 11-bit word PC10 PC8

A M LQID can be used for table lookup or code conversion

such as BCD to seven-segment The LQID instruction

replaces the least significant 8 bits of the PC as follows A

and PC(8) unchanged The ROM data pointed to by the

new address is fetched and loaded into the Q latches Next

the stack is ‘‘popped’’ (SC

storing the saved value of PC to continue sequential pro-

gram execution Since LQID pushes SB

ous contents of SC are lost

Note LQID uses 2 instruction cycles if executed one if

skipped

JID INSTRUCTION

JID (Jump Indirect) is an indirect addressing instruction

transferring program control to a new ROM location pointed

to indirectly by A and M It loads the lower 8 bits of the ROM

address register PC with the contents of ROM addressed by

the 11-bit word PC10 8 A M PC10 PC9 and PC8 are not

affected by JID

Note JID uses 2 instruction cycles if executed one if

skipped

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