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LTC1876

1876fa

then, sub-logic level threshold MOSFETs (VGS(TH) < 3V)

should be used. Pay close attention to the BVDSS specifi-

cation for the MOSFETs as well; most of the logic level

MOSFETs are limited to 30V or less.

Selection criteria for the power MOSFETs include the “ON”

resistance RDS(ON), reverse transfer capacitance CRSS,

input voltage and maximum output current. When the

LTC1876 is operating in continuous mode the duty cycles

for the top and bottom MOSFETs are given by:

Main Switch Duty Cycle

OUT

Synchronous Switch Duty Cycle

OUT

–

The MOSFET power dissipations at maximum output

current are given by:

MAIN

OUT

MAX

DS ON

MAX

RSS

() +

()

() ( )( )( )

()

SYNC

OUT

MAX

DS ON

() +

()

–

()

where

δ is the temperature dependency of RDS(ON) and k

is a constant inversely related to the gate drive current.

Both MOSFETs have I2R losses while the topside N-channel

equation includes an additional term for transition losses,

which are highest at high input voltages. For VIN < 20V the

high current efficiency generally improves with larger

MOSFETs, while for VIN > 20V the transition losses rapidly

increase to the point that the use of a higher RDS(ON) device

with lower CRSS actually provides higher efficiency. The

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during a

short-circuit when the synchronous switch is on close to

100% of the period.

The term (1 +

δ) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs temperature curve, but

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs. CRSS is usually specified in the MOS-

FET characteristics. The constant k = 1.7 can be used to

estimate the contributions of the two terms in the main

switch dissipation equation.

The Schottky diode D1 shown in Figure 1 conducts during

the dead-time between the conduction of the two power

MOSFETs. This prevents the body diode of the bottom

MOSFET from turning on, storing charge during the dead-

time and requiring a reverse recovery period that could

cost as much as 3% in efficiency at high VIN. A 1A to 3A

Schottky is generally a good compromise for both regions

of operation due to the relatively small average current.

Larger diodes result in additional transition losses due to

their larger junction capacitance.

CIN Selection

The selection of CIN is simplified by the multiphase archi-

tecture and its impact on the worst-case RMS current

drawn through the input network (battery/fuse/capacitor).

It can be shown that the worst case RMS current occurs

when only one controller is operating. The controller with

the highest (VOUT)(IOUT) product needs to be used in the

formula below to determine the maximum RMS current

requirement. Increasing the output current, drawn from

the other out-of-phase controller, will actually decrease

the RMS ripple current from this maximum value (see

Figure 4). The out-of-phase technique typically reduces

the input capacitor’s RMS ripple current by a factor of 30%

to 70% when compared to a single phase power supply

solution.

The type of input capacitor, value and ESR rating have

efficiency effects that need to be considered in the selec-

tion process. The capacitance value chosen should be

sufficient to store adequate charge to keep high peak

battery currents down. 20

µF to 40µF is usually sufficient

for a 25W output supply operating at 200kHz. The ESR of

the capacitor is important for capacitor power dissipation

as well as overall battery efficiency. All of the power (RMS

ripple current • ESR) not only heats up the capacitor but

wastes power from the battery.

APPLICATIO S I FOR ATIO

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