LTC1876 datasheet(32/36 Pages) LINER

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LTC1876

1876fa

6. Are the SENSE– and SENSE+ leads routed together with

minimum PC trace spacing? The filter capacitor between

SENSE+ and SENSE– should be as close as possible to the

IC.

7. Is the INTVCC decoupling capacitor connected close to

the IC, between the INTVCC and the power ground pins?

This capacitor carries the MOSFET drivers current peaks.

An additional 1

µF ceramic capacitor placed immediately

next to the INTVCC and PGND pins can help improve noise

performance substantially.

8. Keep the switching nodes (SW1, SW2, AUXSW), top

gate nodes (TG1, TG2), and boost nodes (BOOST1,

BOOST2) away from sensitive small-signal nodes, espe-

cially from the opposites channel’s voltage and current

sensing feedback pins. All of these nodes have very large

and fast moving signals and therefore should be kept on

the “output side” of the LTC1876 and occupy minimum PC

trace area.

9. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on the

same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTVCC

decoupling capacitor, the bottom of the voltage feedback

resistive divider and the SGND pin of the IC.

PC Board Layout Debugging

Start with one regulator on at a time. It is best to first start

with one of the step-down regulator and it is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope

to the internal oscillator and probe the actual output

voltage as well. Check for proper performance over the

operating voltage and current range expected in the

application. The frequency of operation should be main-

tained over the input voltage range down to dropout and

until the output load drops below the low current operation

threshold—typically 10% to 20% of the maximum de-

signed current level in Burst Mode operation.

The duty cycle percentage should be maintained from

cycle to cycle in a well-designed, low noise PCB imple-

mentation. Variation in the duty cycle at a subharmonic

rate can suggest noise pickup at the current or voltage

sensing inputs or inadequate loop compensation. Over-

compensation of the loop can be used to tame a poor PC

layout if regulator bandwidth optimization is not required.

Only after each controller is checked for their individual

performance should both controllers be turned on at the

same time. A particularly difficult region of operation is

when one controller channel is nearing its current com-

parator trip point when the other channel is turning on its

top MOSFET. This occurs around 50% duty cycle on either

channel due to the phasing of the internal clocks and may

cause minor duty cycle jitter.

Short-circuit testing can be performed to verify proper

overcurrent latchoff, or 5

µA can be provided to the

RUN/SS pin(s) by resistors from VIN or INTVCC (depend-

ing upon the STBYMD pin programming), to prevent the

short-circuit latchoff from occurring.

Reduce VIN from its nominal level to verify operation of the

regulator in dropout. Check the operation of the undervolt-

age lockout circuit by further lowering VIN and monitoring

the outputs to verify operation.

Investigate whether any problems exist only at higher

output currents or only at higher input voltages. If prob-

lems coincide with high input voltages and low output

currents, look for capacitive coupling between the BOOST,

SW, TG, and possibly BG connections and the sensitive

voltage and current pins. The capacitor placed across the

current sensing pins needs to be placed immediately

adjacent to the pins of the IC. This capacitor helps to

minimize the effects of differential noise injection due to

high frequency capacitive coupling. If problems are en-

countered with high current output loading at lower input

voltages, look for inductive coupling between CIN, Schot-

tky and the top MOSFET components to the sensitive

current and voltage sensing traces. In addition, investigate

common ground path voltage pickup between these com-

ponents and the SGND pin of the IC.

APPLICATIO S I FOR ATIO

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