LTC1876 datasheet(25/36 Pages) LINER

25 / 36 page

LTC1876

1876fa

quadrupling the importance of loss terms in the switching

regulator system!

4. Transition losses apply only to the topside MOSFET(s),

and only when operating at high input voltages (typically

20V or greater). Transition losses can be estimated from:

Transition Loss = (1.7) VIN2 IO(MAX) CRSS f

Other “hidden” losses such as copper trace and internal

battery resistances can account for an additional 5% to

10% efficiency degradation in portable systems. It is very

important to include these “system” level losses in the

design of a system. The internal battery and fuse resis-

tance losses can be minimized by making sure that CIN has

adequate charge storage and very low ESR at the switch-

ing frequency. A 25W supply will typically require a

minimum of 20

µF to 40µF of capacitance having a maxi-

mum of 20m

Ω to 50mΩ of ESR. The LTC1876 step-down

controllers 2-phase architecture typically halves this input

capacitance requirement over competing solutions. Other

losses including Schottky conduction losses during dead-

time and inductor core losses generally account for less

than 2% total additional loss.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to

∆ILOAD (ESR), where ESR is the effective

series resistance of COUT. ∆ILOAD also begins to charge or

discharge COUT generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recovery

time VOUT can be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values.

The availability of the ITH pin not only allows

optimization of control loop behavior but also provides a

DC coupled and AC filtered closed loop response test

point. The DC step, rise time and settling at this test point

truly reflects the closed loop response. Assuming a pre-

dominantly second order system, phase margin and/or

damping factor can be estimated using the percentage of

overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The ITH

external components shown in the Figure 1 circuit will

provide an adequate starting point for most applications.

The ITH series RC-CC filter sets the dominant pole-zero

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to maximize

transient response once the final PC layout is done and the

particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

feedback factor gain and phase. An output current pulse of

20% to 100% of full-load current having a rise time of 1

µs

to 10

µs will produce output voltage and ITHpinwaveforms

that will give a sense of the overall loop stability without

breaking the feedback loop. The initial output voltage step

resulting from the step change in output current may not

be within the bandwidth of the feedback loop, so this signal

cannot be used to determine phase margin. This is why it

is better to look at the ITH pin signal which is in the

feedback loop and is the filtered and compensated control

loop response. The gain of the loop will be increased by

increasing RC and the bandwidth of the loop will be

increased by decreasing CC. If RC is increased by the same

factor that CC is decreased, the zero frequency will be kept

the same, thereby keeping the phase the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loop system and will demonstrate the actual over-

all supply performance.

A second, more severe transient is caused by switching in

loads with large (>1

µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited to

approximately 25 • CLOAD. Thus a 10µF capacitor would

require a 250

µs rise time, limiting the charging current to

about 200mA.

APPLICATIO S I FOR ATIO

LTC1876 Datasheet(PDF) 25 Page - Linear Technology

LTC1876 Datasheet(HTML) 25 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL