EMC6D103 datasheet(76/89 Pages) SMSC

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Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features

Datasheet

Revision 0.4 (04-04-05)

SMSC EMC6D103

DATASHEET

Bit[1] PWM2/INT# pin select: 0=PWM, 1=INT#

Bit[2] Reserved

Bit[3] TRDY: Temperature Reading Ready. This bit indicates that the temperature reading registers

have valid values. This bit is used after writing the start bit to ‘1’. 0= not valid, 1=valid.

Bit[4] SUREN: Spin-up reduction enable. This bit enables the reduction of the spin-up time based on

feedback from all fan tachometers associated with each PWM. 0=disable, 1=enable (default)

Bit[5] SMSC Reserved

This is an SMSC Reserved bit. Writing this bit to a value different than the default value may cause

unwanted results.

Bit[6] SMSC Reserved

This is an SMSC Reserved bit. Writing this bit to a value different than the default value may cause

unwanted results.

Bit[7] Initialization

Setting the INIT bit to ‘1’ performs a soft reset. This bit is self-clearing. Soft Reset sets all the registers

except the Reading Registers to their default values.

8.2.28

These registers become read only when the Lock bit is set. Any further attempts to write to these

registers shall have no effect.

This register is used to enable individual fan tach error events to set the corresponding status bits in

the interrupt status registers. This register also contains the group fan tach enable bit (Bit[0] TACH),

which is used to enable fan tach events to force the interrupt pin (INT#) low if interrupts are enabled

(see Bit[2] INTEN of the Special Function register at offset 7Ch).

This register contains the following bits:

Bit[0] TACH (Group TACH Enable)

0=Out-of-limit tachometer readings do not affect the state of the INT# pin (default)

1=Enable out-of-limit tachometer readings to make the INT# pin active low

Bit[1] Fan Tach 1 Event Enable

Bit[2] Fan Tach 2 Event Enable

Bit[3] Fan Tach 3 Event Enable

Bit[4] Fan Tach 4 Event Enable

Bit[5] Reserved

Bit[6] Reserved

Bit[7] Reserved

Table 8.46 Register 80h: Interrupt Enable 2 Register

Address

Read/

Write

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

Default

Value

80h

R/W

Interrupt Enable 2 (Fan

Tachs)

RES

TACH4

TACH3

TACH2

TACH1

TACH

1Eh

EMC6D103 Datasheet(PDF) 76 Page - SMSC Corporation

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