LTC7813 datasheet(9/38 Pages) LINER

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LTC3895

3895fa

For more information www.linear.com/LTC3895

pin FuncTions

OVLO (Pin 1): Overvoltage Lockout Input. A voltage on

this pin above 1.2V disables switching of the controller.

TheDRVCCandINTVCCsuppliesmaintainregulationduring

an OVLO event. Exceeding the OVLO threshold triggers a

soft-start reset. If the OVLO function is not used, connect

this pin to GND.

VPRG (Pin 2): Output Voltage Control Pin. This pin sets

the regulator in adjustable output mode using external

feedback resistors or fixed 5V/3.3V output mode. Floating

this pin allows the output to be programmed from 0.8V

to 60V with an external resistor divider on the VFB pin,

regulating VFB to 0.8V. Tying this pin to INTVCC or GND

programs the output to 5V or 3.3V, respectively, through

an internal resistor divider on VFB.

SENSE+ (Pin 3): The (+) Input to the Differential Current

Comparator. The ITH pin voltage and controlled offsets

between the SENSE– and SENSE+ pins in conjunction with

RSENSE set the current trip threshold.

SENSE– (Pin 4): The (–) Input to the Differential Current

Comparator. When SENSE– is greater than INTVCC, the

SENSE– pin supplies power to the current comparator.

SS (Pin 5): Soft-Start Input. The LTC3895 regulates the

VFB voltage to the smaller of 0.8V or the voltage on the

SS pin. An internal 10μA pull-up current source is con-

nected to this pin. A capacitor to ground at this pin sets

the ramp time to final regulated output voltage. The SS

pin is also used for the Regulator Shutdown (REGSD)

feature. A 5μA/1μA pull-down current can be connected

on SS depending on the state of the EXTVCC LDO and the

voltage on SS. See Regulator Shutdown in the Operation

sectionformoreinformation.TodefeattheREGSDfeature,

place a 330k or smaller resistor between INTVCC and SS.

See Soft-Start Pin in the Applications Information section

for more information on defeating REGSD.

VFB (Pin 6): Feedback Input. If the VPRG pin is floating,

the VFB pin receives the remotely sensed feedback volt-

age from an eternal resistor divider across the output. If

VPRG is tied to GND or INTVCC, the VFB pin receives the

remotely sensed output voltage directly.

ITH(Pin7):ErrorAmplifierOutputandSwitchingRegulator

Compensation Point. The current comparator trip point

increases with this control voltage.

MODE (Pin 8): Mode Select and Burst Clamp Adjust In-

put. This input determines how the LTC3895 operates at

light loads. Pulling this pin to ground selects Burst Mode

operation with the burst clamp level defaulting to 25% of

VSENSE(MAX). Tying this pin to a voltage between 0.5V and

1.0V selects Burst Mode operation and adjusts the burst

clamp between 10% and 60%. Tying this pin to INTVCC

forcescontinuousinductorcurrentoperation.Tyingthispin

to a voltage greater than 1.4V and less than INTVCC – 1.3V

selects pulse-skipping operation.

GND (Pins 9, 12, 15, Exposed Pin 39): Ground. All GND

pins must be tied together for operation. The exposed pad

must be soldered to PCB ground for rated electrical and

thermal performance.

CPUMP_EN (Pin 10): Charge Pump Enable Pin for the Top

Gate Driver Boost Supply. Tying this pin to INTVCCenables

the boost supply charge pump and allows for 100% duty

cycle operation in dropout. Tying this pin to GND disables

the charge pump and enables boost refresh, allowing for

99% duty cycle operation in dropout. Do not float this pin.

CLKOUT (Pin 11): Output Clock Signal. This signal is

available to daisy-chain other controller ICs for additional

MOSFET driver stages/phases. The output levels swing

from INTVCC to ground.

PLLIN (Pin 13): External Synchronization Input to Phase

Detector. When an external clock is applied to this pin,

the phase-locked loop will force the rising TG signal to be

synchronized with the rising edge of the external clock. If

the MODE pin is set to Forced Continuous Mode or Burst

Mode operation, then the regulator operates in Forced

Continuous Mode when synchronized. If the MODE pin is

set to pulse-skipping mode, then the regulator operates

in pulse-skipping mode when synchronized.

PGOOD (Pin 14): Open-Drain Logic Output. PGOOD is

pulled to ground when the voltage on the VFB pin is not

within ±10% of its set point.

NC (Pin 16): No connect. Float this pin or connect to GND.

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