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AM3351 Datasheet(PDF) 19 Page - Texas Instruments |
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AM3351 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 252 page  Copyright © 2011–2016, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 19 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 www.ti.com SPRS717J – OCTOBER 2011 – REVISED APRIL 2016 Table 4-2. Pin Attributes (ZCE and ZCZ Packages) ZCE BALL NUMBER [1] ZCZ BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] (25) BALL RESET REL. STATE [7] RESET REL. MODE [8] ZCE POWER / ZCZ POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULLUP /DOWN TYPE [12] I/O CELL [13] B8 B6 AIN0 AIN0 0 A (22) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog A11 C7 AIN1 AIN1 0 A (21) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog A8 B7 AIN2 AIN2 0 A (21) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog B11 A7 AIN3 AIN3 0 A (20) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog C8 C8 AIN4 AIN4 0 A (20) Z Z 0 VDDA_ADC / VDDA_ADC NA 25 NA Analog B12 B8 AIN5 AIN5 0 A Z Z 0 VDDA_ADC / VDDA_ADC NA NA NA Analog A10 A8 AIN6 AIN6 0 A Z Z 0 VDDA_ADC / VDDA_ADC NA NA NA Analog A12 C9 AIN7 AIN7 0 A Z Z 0 VDDA_ADC / VDDA_ADC NA NA NA Analog C13 C10 CAP_VBB_MPU CAP_VBB_MPU NA A D6 D6 CAP_VDD_RTC CAP_VDD_RTC NA A B10 D9 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A D13 D11 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A F3 F3 DDR_A0 ddr_a0 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL J2 H1 DDR_A1 ddr_a1 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL D1 E4 DDR_A2 ddr_a2 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL B3 C3 DDR_A3 ddr_a3 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL E5 C2 DDR_A4 ddr_a4 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL A2 B1 DDR_A5 ddr_a5 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL B1 D5 DDR_A6 ddr_a6 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL D2 E2 DDR_A7 ddr_a7 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL C3 D4 DDR_A8 ddr_a8 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL B2 C1 DDR_A9 ddr_a9 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL E2 F4 DDR_A10 ddr_a10 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL G4 F2 DDR_A11 ddr_a11 0 O H 1 0 VDDS_DDR / VDDS_DDR NA 8 PU/PD LVCMOS/SSTL/ HSTL |
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