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AM3351 Datasheet(PDF) 202 Page - Texas Instruments |
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AM3351 Datasheet(HTML) 202 Page - Texas Instruments |
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202 / 252 page  202 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 SPRS717J – OCTOBER 2011 – REVISED APRIL 2016 www.ti.com Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 Peripheral Information and Timings Copyright © 2011–2016, Texas Instruments Incorporated 7.10.2 LCD Raster Mode Table 7-76. Switching Characteristics for LCD Raster Mode (see Figure 7-82 through Figure 7-85) NO. PARAMETER OPP50 OPP100 UNIT MIN MAX MIN MAX 1 tc(LCD_PCLK) Cycle time, pixel clock 15.8 7.9 ns 2 tw(LCD_PCLKH) Pulse duration, pixel clock high 0.45tc 0.55tc 0.45tc 0.55tc ns 3 tw(LCD_PCLKL) Pulse duration, pixel clock low 0.45tc 0.55tc 0.45tc 0.55tc ns 4 td(LCD_PCLK-LCD_DATAV) Delay time, LCD_PCLK to LCD_DATA[23:0] valid (write) 3.0 1.9 ns 5 td(LCD_PCLK-LCD_DATAI) Delay time, LCD_PCLK to LCD_DATA[23:0] invalid (write) –3.0 –1.7 ns 6 td(LCD_PCLK-LCD_AC_BIAS_EN) Delay time, LCD_PCLK to LCD_AC_BIAS_EN –3.0 3.0 –1.7 1.9 ns 7 tt(LCD_AC_BIAS_EN) Transition time, LCD_AC_BIAS_EN 0.5 2.4 0.5 2.4 ns 8 td(LCD_PCLK-LCD_VSYNC) Delay time, LCD_PCLK to LCD_VSYNC –3.0 3.0 –1.7 1.9 ns 9 tt(LCD_VSYNC) Transition time, LCD_VSYNC 0.5 2.4 0.5 2.4 ns 10 td(LCD_PCLK-LCD_HSYNC) Delay time, LCD_PCLK to LCD_HSYNC –3.0 3.0 –1.7 1.9 ns 11 tt(LCD_HSYNC) Transition time, LCD_HSYNC 0.5 2.4 0.5 2.4 ns 12 tt(LCD_PCLK) Transition time, LCD_PCLK 0.5 2.4 0.5 2.4 ns 13 tt(LCD_DATA) Transition time, LCD_DATA 0.5 2.4 0.5 2.4 ns Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1) register: • Vertical front porch (VFP) • Vertical sync pulse width (VSW) • Vertical back porch (VBP) • Lines per panel (LPP_B10 + LPP) Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register: • Horizontal front porch (HFP) • Horizontal sync pulse width (HSW) • Horizontal back porch (HBP) • Pixels per panel (PPLMSB + PPLLSB) LCD_AC_BIAS_EN timing is derived through the following parameter in the LCD (RASTER_TIMING_2) register: • AC bias frequency (ACB) The display format produced in raster mode is shown in Figure 7-81. An entire frame is delivered one line at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the activation of I/O signal LCD_HSYNC. |
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