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AD8318

Rev. 0 | Page 11 of 24

GENERAL DESCRIPTION

The AD8318 is a 9-stage demodulating logarithmic amplifier,

which provides RF measurement and power amplifier control

functions. The design is similar to the AD8313 Logarithmic

Detector/Controller. However, the AD8318 input frequency

range is extended to 8 GHz with 60 dB dynamic range. Other

improvements include: reduced intercept variability versus

temperature, increased dynamic range at higher frequencies, low

noise measurement and controller output (VOUT), adjustable

low-pass corner frequency (CLPF), temperature sensor output

(TEMP), negative transfer function slope for higher accuracy,

and 10 ns response time for RF burst detection capability. A

block diagram is shown in Figure 21.

TEMP

SENSOR

GAIN

BIAS

SLOPE

DET

INHI

INLO

VOUT

VSET

CLPF

TEMP

VPSI

ENBL

TADJ

VPSO

CMOP

CMIP

Figure 21. Block Diagram

A fully differential design, using a proprietary high speed

SiGe process, extends high frequency performance. Input INHI

receives the signal with a low frequency impedance of nominally

1200 Ω in parallel with 0.7 pF. The maximum input with ±1 dB

log-conformance error is typically 0 dBm (re: 50 Ω). The noise

spectral density referred to the input is 1.15 nV/√Hz, which

is equivalent to a voltage of 118 µV rms in a 10.5 GHz band-

width, or a noise power of –66 dBm (re: 50 Ω). This noise

spectral density sets the lower limit of the dynamic range.

However, the low-end accuracy of the AD8318 is enhanced

by specially shaping the demodulating transfer characteristic

to partially compensate for errors due to internal noise. The

input system common pin, CMIP, provides a quality low

impedance connection to the printed circuit board (PCB)

ground through the use of four package pins. The package

paddle, which is internally connected to the CMIP pin, should

also be grounded to the PCB to reduce thermal impedance from

the die to the PCB.

The logarithmic function is approximated in a piecewise fashion

by 9 cascaded gain stages. (For a more comprehensive expla-

nation of the logarithm approximation, please refer to the

AD8307 data sheet, available at www.analog.com.) The cells have

a nominal voltage gain of 8.7 dB each, and a 3 dB bandwidth of

10.5 GHz. Using precision biasing, the gain is stabilized over

temperature and supply variations. Since the cascaded gain

stages are dc-coupled, the overall dc gain is high. An offset

compensation loop is included to correct for offsets within

the cascaded cells. At the output of each of the gain stages, a

square-law detector cell is used to rectify the signal. The RF

signal voltages are converted to a fluctuating differential

current having an average value that increases with signal

level. Along with the nine gain stages and detector cells, an

additional detector is included at the input of the AD8318,

altogether providing a 60 dB dynamic range. After the

detector currents are summed and filtered, the function

ID × log10(VIN/VINTERCEPT) is formed at the summing node,

where ID is the internally set detector current, VIN is the

input signal voltage, and VINTERCEPT is the intercept voltage

(i.e., when VIN = VINTERCEPT, the output voltage would be 0 V,

if it were capable of going to 0 V).

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