AD8318 datasheet(12/24 Pages) AD

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AD8318

Rev. 0 | Page 12 of 24

USING THE AD8318

BASIC CONNECTIONS

The AD8318 is specified for operation up to 8 GHz, as a result

low impedance supply pins with adequate isolation between

functions are essential. In the AD8318, the two positive supply

pins, VPSI and VPSO, must be connected to the same potential.

The VPSI pin biases the input circuitry, while the VPSO biases

the low noise output driver for VOUT. Separate commons are

also included in the device. CMOP is used as the common for

the output drivers. All commons should be connected to a low

impedance ground plane.

A power supply voltage of between 4.5 V and 5.5 V should be

applied to VPS0 and VPS1. 100 pF and 0.1 µF power supply

decoupling capacitors should be connected close to each power

supply pin. (The two adjacent VPS1 pins can share a pair of

decoupling capacitors because of their proximity.)

CMIP

TADJ

VPSO

CMIP

VPSI

TEMP

CMOP

INHI

VSET

INLO

VOUT

ENBL

CLPF

AD8318

100pF

0.1

µF

1nF

499

Ω

(SEE TEXT)

100pF

0.1

µF

52.3

Ω

TEMP

OUT

INPUT

VOUT

Figure 22. Basic Connections

The paddle of the AD8318’s LFCSP package is internally

connected to CMIP. For optimum thermal and electrical

performance, the paddle should be soldered to a low impedance

ground plane.

ENABLE

To enable the AD8318, the ENBL pin must be pulled high.

Taking ENBL low will put the AD8318 in sleep mode, reducing

current consumption to 260 µA at ambient. The voltage on

ENBL must be greater than 2 VBE (~1.7 V) to enable the device.

When enabled the devices draws less than 1 µA. When the ENBL

pin is pulled low, the pin sources 15 µA.

The enable interface has high input impedance. A 200 Ω resistor

is placed in series with the ENBL input for added protection.

Figure 23 depicts a simplified schematic of the enable interface.

ENBL

CMIP

VPSI

× V

DISCHARGE

ENABLE

40k

Ω

200

Ω

40k

Ω

Figure 23. ENBL Interface

INPUT SIGNAL COUPLING

The RF input to the AD8318 (INHI) is single-ended and

must be ac-coupled. INLO (input common) should be

ac-coupled to ground (See Figure 22). Suggested coupling

capacitors are 1 nF ceramic 0402 style capacitors for input

frequencies of 1 MHz to 8 GHz. The coupling capacitors

should be mounted close to the INHI and INLO pins. These

capacitor values can be increased to lower the input stage’s

high-pass cutoff frequency. The high-pass corner is set by

the input coupling capacitors and the internal 10 pF high-

pass capacitor. The dc voltage on INHI and INLO will be

about one diode voltage drop below VPSI.

The Smith chart in Figure 15 shows the AD8318’s input

impedance vs. frequency. Table 4 lists the reflection coeffi-

cient and impedance at select frequencies. For Figure 15 and

Table 4, the 52.3 Ω input termination resistor was removed.

At dc, the resistance is typically 2 kΩ. At frequencies up to 1

GHz, the impedance is approximated as 1000 Ω || 0.7 pF.

The RF input pins are coupled to a network given by the

simplified schematic in Figure 24.

VPSI

Ω

A = 8.6dB

20k

Ω

20k

Ω

CURRENT

STAGE

INLO

INHI

OFFSET

COMP

10pF

FIRST

GAIN

STAGE

Figure 24. Input Interface

While the input can be reactively matched, in general this is

not necessary. An external 52.3 Ω shunt resistor (connected

on the signal side of the input coupling capacitors, see

Figure 22) combines with the relatively high input imped-

ance to give an adequate broadband 50 Ω match.

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