CDCM7005 datasheet(6/40 Pages) TI

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Package Thermal Resistance for RGZ (QFN) Package

(1) (2)

Package Thermal Resistance for ZVA (BGA) Package

(1)

RECOMMENDED OPERATING CONDITIONS

TIMING REQUIREMENTS

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

Airflow (lfm)

JA (°C/W)

JC (°C/W)

JP (°C/W)

(3)

JT (°C/W)

29.9

22.4

1.5

0.2

150

24.7

0.2

250

23.2

0.2

500

21.5

0.3

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(2)

Connected to GND with nine thermal vias (0,3 mm diameter).

(3)

JP (junction pad) is used for the QFN package, because the main heat flow is from the junction to the GND pad of the QFN.

Airflow (m/s)

JA (°C/W)

JC (°C/W)

JB (°C/W)

(2)

JT (°C/W)

0 m/s

53.9

28.3

38.6

0.7

1 m/s

49.8

0.7

2 m/s

48.5

0.8

(1)

The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).

(2)

JB (junction board) is used for the BGA package, because the main heat flow is from junction to the board.

MIN

NOM

MAX

UNIT

VCC, AVCC

3.3

3.6

Supply voltage

VCC_CP

2.3

VCC

VIL

Low-level input voltage LVCMOS, see (1)

0.3 VCC

VIH

High-level input voltage LVCMOS, see (1)

0.7 VCC

IOH

High-level output current LVCMOS (includes all status pins)

–8

IOL

Low-level output current LVCMOS (includes all status pins)

Input voltage range LVCMOS

3.6

VIL

Low-level input voltage LVPECL

VCC–1.81

VCC–1.475

VIH

High-level input voltage LVPECL

VCC–1.26

VCC–0.88

VINPP

Input amplitude LVPECL (VVCXO_IN– VVCXO_IN)(2)

0.5

1.3

VIC

Common-mode input voltage LVPECL

VCC–0.3

Operating free-air temperature

–40

°C

(1)

VIL and VIH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an ac-coupling to

VCC/2 is provided.

(2)

VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP

of 150 mV.

over recommended ranges of supply voltage, load and operating free air temperature

PARAMETER

MIN

TYP

MAX

UNIT

PRI_REF/SEC_REF_IN REQUIREMENTS

fREF_IN

LVCMOS primary or secondary reference clock frequency(1)(2)

200

MHz

tr/ tf

Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of VCC

dutyREF

Duty cycle of PRI_REF or SEC_REF at VCC/2

40%

60%

VCXO_IN, VCXO_IN REQUIREMENTS

fVCXO_IN

VCXO clock frequency(3)

2200

MHz

(1)

At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the

STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.

(2)

fREF_IN can be up to 250 MHz in typical operating mode (25°C / 3.3-V VCC).

(3)

If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency

detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This

effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!

CDCM7005 Datasheet(PDF) 6 Page - Texas Instruments

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