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T0063-01

PRI_REF

SEC_REF

Internal

Reference Clock

Yx Output

PRI_SEC_CLK

1

1

2

2

3

4

Primary Clock

Secondary Clock

Primary Clock

PLL Lock for Analog and Digital Detect

T0064-01

t

(lockdetect)

Selected REF at PFD

(clock fed through M Divider and M Delay)

VCXO_IN at PFD

(clock fed through N Divider and N Delay)

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

Figure 16. Phase Approach of Output to New Reference Clock

The CDCM7005 supports two PLL lock indications: the digital lock signal or the analog lock signal. Both signals

indicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition.

PLL Lock/Out-of-Lock Definition

The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and

Feedback Clock (VCXO_IN clock) at the PFD (phase frequency detect) are inside a predefined lock detect

window, or if no cycle-slip appears, for a pre-defined number of successive clock cycles.

The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and

Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window or if a cycle-slip

appears.

Both, the lock detect window and the number of successive clock cycles are user definable (Word 3, Bit 2-6).

Figure 17. Lock Detect Window

The lock detect window describes the maximum allowed time difference for lock detect between the rising edge

of PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. The

rising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lock

detect window if there is a phase displacement of more than +0.5

× t

Digital vs Analog Lock

Figure 18 and Figure 19 show the circuit for the digital and analog lock. The analog lock operates with an

external load capacitor.

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