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CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

DEVICE CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

LVCMOS input current for PD, RESET,

HOLD, REF_SEL, PRI_REF,

5

µA

LVCMOS input current for PD, RESET,

HOLD, REF_SEL, PRI_REF,

–15

–35

µA

High-level output voltage for LVCMOS

V

outputs

2.4

2

0.1

Low-level output voltage for LVCMOS

V

outputs

0.5

0.8

High-level output current

–30

mA

Low-level output current

33

mA

tpho

1.8

ns

see Figure 11, Load = 10 pF

LVCMOS pulse skew, see Figure 10

150

ps

Propagation delay from VCXO_IN to

Load = 10 pF, see Figure 12 (PLL

2

2.5

3

ns

Yx, see Figure 10

bypass mode)

All outputs have the same divider ratio

55

LVCMOS single-ended output skew,

ps

Outputs have different divider ratios

70

Duty cycle

LVCMOS

49%

51%

20% to 80% of swing (load

Output rise/fall slew rate

2.4

3.5

V/ns

see Figure 12)

LVPECL

Load, see Figure 13

0

1500

MHz

LVPECL input current

±20

µA

LVPECL high-level output voltage

Load, See Figure 13

V

LVPECL low-level output voltage

Load, See Figure 13

V

Differential output voltage

See Figure 9 and load, see Figure 13

500

mV

–200

100

ps

see Figure 11

Propagation delay time, VCXO_IN to

Cross point-to-cross point, load

340

490

640

ps

Yx, see Figure 10

see Figure 13

Cross point-to-cross point, load

LVPECL pulse skew, see Figure 10

10

ps

see Figure 13

Load see Figure 13, all outputs have the

20

same divider ratio

ps

Load see Figure 13, outputs have

50

different divider ratios

Rise and fall time

120

170

220

ps

Input capacitance at VCXO_IN,

1.5

pF

VCXO_IN

LVCMOS-TO-LVPECL

Output skew between LVCMOS and

1.7

2

2.4

ns

see Figure 12 and Figure 13

(4)

These inputs have an internal 150-k

Ω pullup resistor.

(5)

This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M

and VCXO delay N).

(6)

(7)

Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output

signal swing may no longer meet the output specification.

(8)

The phase of LVCMOS is lagging in reference to the phase of LVPECL.

8