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Charge Pump Current Direction

T0076-01

PFD Pulse

Width Delay

PFD Pulse

Width Delay

0 V

V

CC

PRI_REF or SEC_REF

Clock Fed Through the

M Divider and Delay

VCXO_IN Clock Fed Through

the N Divider and Delay

CP_DIR (Bit 2 of Word 2 = 0,

Default State)

CP_DIR (Bit 2 of Word 2 = 1)

V

(Internal Signal)

(PFD1)

V

(Internal Signal)

(PFD2)

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

The direction of the charge pump (CP) current pulse can be changed by the SPI register (word 2, bit 2). It

determines in which direction the CP current regulates (reference clock leads to feedback clock). Most

applications use the positive CP output current (power-up condition) because of the use of a passive loop filter.

The negative CP current is useful when using an active loop filter concept with inverting operational amplifier.

Figure 23 shows the internal PFD signal and the corresponding CP current.

NOTE: The purpose of the PFD pluse width delay is to improve spurious suppression.

Figure 23. Charge Pump Current Direction (VCXO and VCO Support)

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