www.ti.com

FEATURE DESCRIPTION

Automatic/Manual Reference Clock Switching

T0062-01

PRI_REF

SEC_REF

STATUS_REF

PRI_SEC_CLK

1

2

1

2

3

4

Internal

Reference Clock

Primary Clock

Secondary Clock

Primary Clock

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

YxMUX2

YxMUX1

YxMUX0

Selected Divided V(C)XO Signal for the

Default

Yx Outputs

1

1

0

1

1

1

Div by 8

(1)

This divider setting depends on the selected P-divider mode for the “Div-by-16” divider. In the default mode (after power up), Div-by-16

is selected. But if bit 30 or bit 31 of word 1 is set to [1], then the Div-by-4 and 90 degree phase shift or Div-by-8 and 90 degree phase

shift is selected.

The CDCM7005 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary clock

input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected by the

dedicated SPI register bit (Word 0, Bit 30).

In the manual mode, the external REF_SEL signal selects one of the two input clocks:

REF_SEL [1] -> primary clock is selected

REF_SEL [0] -> secondary clock is selected

In the automatic mode, the primary clock is selected by default even if both clocks are available. In case the

primary clock is not available or fails, then the input switches to the secondary clock as long until the primary

clock is back. Figure 15 shows the automatic clock selection.

NOTE: PRI_REF is the preferred clock input.

Figure 15. Behavior of STATUS_REF and PRI_SEC_CLK

In the automatic mode, the frequencies of both clock signals have to be similar, but may differ by up to 20%. The

phase of the clock signal can be any.

The clock input circuitry is design to suppress glitches during switching between the primary and secondary clock

in the manual and automatic mode. This avoids an undefined switching of the following circuitries.

The phase of the output clock slowly follows the new input phase. There will be no phase-jump at the output.

How quick the phase adjustment is done depends on the selected loop parameter, i.e., at a loop bandwidth of

<100 Hz; the phase adjustment can take several ms. There is no phase build-out function supported (like in

SONET/SDH applications).

25