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F0004-01

No

No

No

PLL

Out-of-Lock?

PLL-Lock

Output

Set?

3-State Charge-Pump

Reference Clock

Back?

64 PFD

Lock-Cycles

Yes

Yes

Yes

Charge-Pump is switched into 3-State.

P-divider and Yx output are at normal operation.

The Charge-Pump remains in 3-State

until the Reference Clock is back. The 1st

valid Reference Clock at the PFD releases

the Charge-Pump.

The PLL acquire 64 lock cycles to phase

align to the input clock.

Frequency Hold-Over Function works in

combination with the Analog Lock-Detect

function only!

Start

PLL is out-of-lock if the phase

difference of Reference Clock and

Feedback Clock at PFD are outside the

predefined Lock-Detect-Window or if a

Cycle-Slip occurs.

PLL has to be in LOCK to start

HOLD-Function.

(The Analog Lock output is not reset by the first Out-of-

Lock event. It stays ‘High’ depending on the analog time

delay (output C-load). The time delay must be long enough

to assure proper HOLD function)

(The ‘PLL-Lock Output Set?’ enquiry can be bypassed by

setting the HOLDTR bit to [1] (Word 3, Bit 11)

Charge Pump Preset to VCC_CP/2

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

Figure 22. Frequency HOLD-Over Function

The preset charge pump to VCC_CP/2 is a useful feature to quickly set the center frequency of the VC(X)O after

powerup or reset. The adequate control voltage for the VC(X)O will be provided to the charge-pump output by an

internal voltage divider of 1 k

Ω/1 kΩ to VCC_CP and GND (VCC_CP/2).

This feature helps to get the initial frequency accuracy, i.e. required at CPRI (Common Public Radio Interface) or

OBSAI (Open Base Station Architecture Initiative).

The preset charge pump to VCC_CP/2 can be set and reset by SPI register (word 2, bit 3). This feature must be

disabled for PLL locking.

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