www.ti.com

S0080-01

Power_Down

Lock_Out

Lock_In

80kW

5pF

PLL_LOCK

Output

Lock

t

Digital Lock Detection

V

= 0.55 V

high

CC

V

= 0.35 V

low

CC

Out-of-Lock

V

Out

S0081-01

Power_Down

Lock_Out

Lock_In

100 A

(Lock)

m

100 A

(Out-of-Lock)

m

80kW

5pF

C

PLL_LOCK

Output

t

V

= 0.55 V

high

CC

V

CC

V

= 0.35 V

low

CC

V

Out

V

= 1/C

I

t

Out

´ ´

Example:

for I = 110 A, C = 10nF, V

= 3.3 V,

and V

= V

= 0.55

Vcc = 1.8V

t = 164 s

m

´

³

m

CC

high

out

Differential LVPECL Outputs and Single-Ended LVCMOS Outputs

CDCM7005

SCAS793A – JUNE 2005 – REVISED JUNE 2005

When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out of

lock until a stable lock is detected. A single low-to-high step can be reached with a wide lock detect window and

high number of successive clock cycles. PLL_LOCK returns to out of lock if just one cycle is outside the lock

detect window or a cycle slip occurs.

Figure 18. Digital Lock-Detect

When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110-µA

current source until logic high-level is reached. Therefore, more time is needed to detect logic high level, but

jittering of PLL_LOCK will be suppressed in case of digital lock. The time PLL_LOCK needs to return to out of

Figure 19. Analog Lock-Detect

The CDCM7005 supports up to 5

× LVPECL outputs or 10 × LVCMOS/LVTTL outputs or any combination of

these. The single-ended LVCMOS outputs are arranged in pairs which mean both outputs of a LVCMOS pair

have the same frequency but can separately be disabled or inverted. The power up output arrangement is five

LVPECL (default setting).

27