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AD9558

Data Sheet

Rev. C | Page 40 of 105

CLOCK DISTRIBUTION

FROM APLL

(3.35GHz TO 4.05GHz)

÷M1

OUT1

OUT2

MAX

1.25GHz

MAX

1.25GHz

÷M2

DIVIDER 1

÷3 TO ÷11

DIVIDER 2

÷3 TO ÷11

FRAME SYNC

MODE ONLY

÷M0

OUT0

÷M3

OUT4

OUT3

÷M3b

OUT5

×2

CHANNEL

SYNC

BLOCK

FRAME

SYNC

BLOCK

CHIP RESET

SELECTED INPUT FRAME PULSE

SYNC SIGNAL TO

M0 TO M3 DIVIDERS

FRAME SYNC

FRAME SYNC ENGAGED SIGNAL

FRAME

SYNC

MONITOR

SYNC/SOFT_SYNC

FSYNC_ALIGN_METHOD

Figure 43. Clock Distribution Block Diagram

RF DIVIDERS (RF DIVIDER 2 AND RF DIVIDER 1)

The first block in each clock distribution section is the RF divider.

The RF dividers divide the VCO output frequency down to a

maximum frequency of ≤1.25 GHz and has special circuitry to

maintain a 50% duty cycle for any divide ratio.

The following register addresses contain the RF divider settings:

•

RF Divider 1: Register 0x0407, Bits[3:0]

•

RF Divider 2: Register 0x0407, Bits[7:4]

In normal operation, the RF dividers do not need to be reset

because the APLL VCO calibration (which normally occurs after

programming the RF divider) automatically performs an

RF divider reset.

However, in cases where the user wants to change either of the

RF dividers, but not recalibrate the corresponding APLL VCO

afterward, the user must first reset that RF divider by writing

0x0F to the appropriate RF divider register and then issuing an

I/O update by writing Register 0x0005 = 0x01. At this point, the

user can program the new RF divider value, and issue another

I/O update.

CHANNEL DIVIDERS

The channel divider blocks, M0, M1, M2, M3, and M3b, are

10-bit integer dividers with a divide range of 1 to 1023. The

channel divider block contains duty cycle correction that

guarantees 50% duty cycle for both even and odd divide ratios.

OUTPUT POWER-DOWN

The output drivers can be individually powered down.

OUTPUT ENABLE

Each of the output channels offers independent control of enable/

disable functionality via the distribution enable register. The

distribution outputs use synchronization logic to control

enable/disable activity to avoid the production of runt pulses

and to ensure that outputs with the same divide ratios become

active/inactive in unison.

OUTPUT MODE

The user has independent control of the operating mode of each of

the four output channels via the output clock distribution registers

(Address 0x0500 to Address 0x0515). The operating mode

control includes

•

Logic family and pin functionality

•

Output drive strength

•

Output polarity

•

Divide ratio

•

Phase of each output channel

Channel 0 and Channel 3 provide 3.3 V CMOS and 1.8 V CMOS

modes. Channel 1 and Channel 2 have 1.8 V CMOS, LVDS, and

HSTL modes.

All CMOS drivers feature a CMOS drive strength that allows

the user to choose between a strong, high performance CMOS

driver or a lower power setting with less EMI and crosstalk. The

best setting is application dependent.

For applications where LVPECL levels are required, the user

must choose the HSTL mode and ac couple the output signal.

See the Input/Output Termination Recommendations section

for recommended termination schemes.

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