AD9558 datasheet(30/105 Pages) AD

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AD9558

Data Sheet

Rev. C | Page 30 of 105

Program the Digital Phase-Locked Loop (DPLL)

The DPLL parameters reside in Register 0x0300 to

•

Free run frequency

•

DPLL pull-in range limits

•

DPLL closed-loop phase offset

•

Phase slew control (for hitless reference switching)

•

Tuning word history control (for holdover operation)

Program the Reference Inputs

The reference input parameters reside in Register 0x0600 to

details on programming these functions. They include the

following:

•

Reference power-down

•

Reference logic family

•

Reference priority

Program the Reference Profiles

The reference profile parameters reside in Register 0x0700 to

wizard that calculates these values based on the user input

frequency. See the Reference Profiles section for details on

programming these functions. They include the following:

•

Reference period

•

Reference period tolerance

•

Reference validation timer

•

Selection of high phase margin loop filter coefficients

•

DPLL loop bandwidth

•

Reference prescaler (R divider)

•

Feedback dividers (N1, N2, N3, FRAC1, and MOD1)

•

Phase and frequency lock detector controls

Generate the Reference Acquisition

After the registers are programmed, the user can clear the user

free run bit (Register 0x0A01, Bit 5) and issue an I/O update,

using Register 0x0005, Bit 0, to invoke all of the register settings

that are programmed up to this point.

After the registers are programmed, the DPLL locks to the first

available valid reference that has the highest priority.

AD9558 Datasheet(PDF) 30 Page - Analog Devices

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