AD9558 datasheet(7/105 Pages) AD

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Data Sheet

AD9558

Rev. C | Page 7 of 105

LOGIC OUTPUTS (M7 TO M0, IRQ)

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC OUTPUTS (M7 to M0, IRQ)

Output High Voltage (VOH)

DVDD3 − 0.4

IOH = 1 mA

Output Low Voltage (VOL)

0.4

IOL = 1 mA

IRQ Leakage Current

Open-drain mode

Active Low Output Mode

−200

µA

VOH = 3.3 V

Active High Output Mode

100

µA

VOL = 0 V

SYSTEM CLOCK INPUTS (XOA, XOB)

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SYSTEM CLOCK MULTIPLIER

Output Frequency Range

750

805

MHz

The VCO range may place limitations on

nonstandard system clock input

frequencies

Phase Frequency Detector (PFD) Rate

150

MHz

Frequency Multiplication Range

255

Assumes valid system clock and PFD

rates

SYSTEM CLOCK REFERENCE INPUT PATH

Input Frequency Range

600

MHz

Minimum Input Slew Rate

V/µs

Minimum limit imposed for jitter

performance

Common-Mode Voltage

1.05

1.16

1.25

Internally generated

Differential Input Voltage Sensitivity

250

mV p-p

Minimum voltage across pins required

to ensure switching between logic

states; the instantaneous voltage on

either pin must not exceed the supply

rails; can accommodate single-ended

input by ac grounding of complementary

input; 1 V p-p recommended for optimal

jitter performance

System Clock Input Doubler Duty Cycle

This is the amount of duty cycle

variation that can be tolerated on the

system clock input to use the doubler

System Clock Input = 50 MHz

System Clock Input = 20 MHz

System Clock Input = 16 MHz to 20 MHz

Input Capacitance

Single-ended, each pin

Input Resistance

4.2

kΩ

CRYSTAL RESONATOR PATH

Crystal Resonator Frequency Range

MHz

Fundamental mode, AT cut crystal

Maximum Crystal Motional Resistance

100

Ω

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