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AD9558 Datasheet(PDF) 65 Page - Analog Devices |
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AD9558 Datasheet(HTML) 65 Page - Analog Devices |
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65 / 105 page  Data Sheet AD9558 Rev. C | Page 65 of 105 Reg Addr (Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0 Def 0x0210 Watchdog Timer 1 Watchdog timer (ms), Bits[7:0] 00 0x0211 Watchdog timer (ms), Bits[15:8] 00 0x0300 Free run frequency TW 30-bit free run frequency tuning word[7:0] 11 0x0301 30-bit free run frequency tuning word[15:8] 15 0x0302 30-bit free run frequency tuning word[23:16] 64 0x0303 Reserved 30-bit free run frequency tuning word[29:24] 1B 0x0304 Digital oscillator control Reserved DCO 4-level output Reserved (must be 1b) Reserved Reset SDM 10 0x0305 Reserved 00 0x0306 DPLL frequency clamp Lower limit of pull-in range[7:0] 51 0x0307 Lower limit of pull-in range[15:8] B8 0x0308 Reserved Lower limit of pull-in range[19:16] 02 0x0309 Upper limit of pull-in range[7:0] 3E 0x030A Upper limit of pull-in range[15:8] 0A 0x030B Reserved Upper limit of pull-in range[19:16] 0B 0x030C Closed-loop phase lock offset (±0.5 ms) Fixed phase lock offset (signed; ps), Bits[7:0] 00 0x030D Fixed phase lock offset (signed; ps), Bits[15:8] 00 0x030E Fixed phase lock offset (signed; ps), Bits[23:16] 00 0x030F Reserved Fixed phase lock offset (signed; ps), Bits[29:24] 00 0x0310 Incremental phase lock offset step size (ps/step), Bits[7:0] (up to 65.5 ns/step) 00 0x0311 Incremental phase lock offset step size (ps/step), Bits[15:8] (up to 65.5 ns/step) 00 0x0312 Phase slew rate limit Phase slew rate limit (µs/sec), Bits[7:0] (315 µs/sec up to 65.536 ms/sec) 00 0x0313 Phase slew rate limit (µs/sec), Bits[15:8] (315 µs/sec up to 65.536 ms/sec) 00 0x0314 Holdover history History accumulation timer (ms), Bits[7:0] (up to 65 seconds) 0A 0x0315 History accumulation timer (ms), Bits[15:8] (up to 65 seconds) 00 0x0316 History mode Reserved Single sample fallback Persistent history Incremental average 00 0x0317 L Base Loop Filter A coefficient set (high phase margin) HPM Alpha-0[7:0] 8C 0x0318 L HPM Alpha-0[15:8] AD 0x0319 L Reserved HPM Alpha-1[6:0] 4C 0x031A L HPM Beta-0[7:0] F5 0x031B L HPM Beta-0[15:8] CB 0x031C L Reserved HPM Beta-1[6:0] 73 0x031D L HPM Gamma-0[7:0] 24 0x031E L HPM Gamma-0[15:8] D8 0x031F L Reserved HPM Gamma-1[6:0] 59 0x0320 L HPM Delta-0[7:0] D2 0x0321 L HPM Delta-0[15:8] 8D 0x0322 L Reserved HPM Delta-1[6:0] 5A 0x0323 L Base loop Filter A coefficient set (normal phase margin of 70º) NPM Alpha-0[7:0] 24 0x0324 L NPM Alpha-0[15:8] 8C 0x0325 L Reserved NPM Alpha-1[6:0] 49 0x0326 L NPM Beta-0[7:0] 55 0x0327 L NPM Beta-0[15:8] C9 0x0328 L Reserved NPM Beta-1[6:0] 7B 0x0329 L NPM Gamma-0[7:0] 9C 0x032A L NPM Gamma-0[15:8] FA 0x032B L Reserved NPM Gamma-1[6:0] 55 0x032C L NPM Delta-0[7:0] EA 0x032D L NPM Delta-0[15:8] E2 0x032E L Reserved NPM Delta-1[6:0] 57 Output PLL (APLL) 0x0400 APLL charge pump Output PLL (APLL) charge pump[7:0] 81 0x0401 APLL N divider Output PLL (APLL) feedback N divider[7:0] 14 0x0402 Reserved 00 0x0403 APLL loop filter control APLL loop filter control[7:0] 07 0x0404 Reserved Bypass internal RZERO 00 |
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